From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id D34EB42A02;
Wed, 26 Apr 2023 12:28:18 +0200 (CEST)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id E513E42D33;
Wed, 26 Apr 2023 12:28:02 +0200 (CEST)
Received: from mga17.intel.com (mga17.intel.com [192.55.52.151])
by mails.dpdk.org (Postfix) with ESMTP id 65DF542D1D;
Wed, 26 Apr 2023 12:28:00 +0200 (CEST)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple;
d=intel.com; i=@intel.com; q=dns/txt; s=Intel;
t=1682504880; x=1714040880;
h=from:to:cc:subject:date:message-id:in-reply-to:
references:mime-version:content-transfer-encoding;
bh=FLOzSIp7OeQRV7sspPldHGbBKpUSnbSBjVpl2JmpW0Y=;
b=QoKUbHGAe+WXsuczbipSOJkwkRIOcmIhAD8UZtzkYmjlbtNmVHMwsdhp
f+AHHcQEwOky08/uwpNP19pVpycb06VTgg7gDPX/DRAidkINIJcvnEsVs
XFj/9CoSX/V+lbiFjEZh5osERV1MCIYXugS3bBoz/THoXeMDLMUaMhFEV
3/ovI5AjdVrkyubRdm1fY2g7xxXe9KfFeCQyFv70Bfw0EHNovUijN9VtU
FjvBhmb6Il6FivhkS+hM/c/jpTKBKq8aiibA8Ymigc0ADRAULFzbpmj5l
pCR4oZ8NNmAy5D44VoUUWutPlX557z2sr6HIVebVX2jk79t7sA3WwhKfQ A==;
X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391501"
X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391501"
Received: from fmsmga005.fm.intel.com ([10.253.24.32])
by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
26 Apr 2023 03:27:57 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552640"
X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552640"
Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239])
by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:27:55 -0700
From: Wenjing Qiao <wenjing.qiao@intel.com>
To: jingjing.wu@intel.com,
beilei.xing@intel.com,
qi.z.zhang@intel.com
Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao <wenjing.qiao@intel.com>,
stable@dpdk.org, Priyalee Kushwaha <priyalee.kushwaha@intel.com>
Subject: [PATCH v3 03/15] common/idpf/base: fix ITR register definitions for
AVF
Date: Wed, 26 Apr 2023 06:22:47 -0400
Message-Id: <20230426102259.205992-4-wenjing.qiao@intel.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com>
References: <20230421084043.135503-2-wenjing.qiao@intel.com>
<20230426102259.205992-1-wenjing.qiao@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Fix ITR register definitions for AVF1.0 and AVF2.0
Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")
Cc: stable@dpdk.org
Signed-off-by: Priyalee Kushwaha <priyalee.kushwaha@intel.com>
Signed-off-by: Wenjing Qiao <wenjing.qiao@intel.com>
---
drivers/common/idpf/base/idpf_lan_pf_regs.h | 9 +++++++--
drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++-----
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 3df2347bd7..7f731ec3d6 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -77,8 +77,13 @@
#define PF_GLINT_DYN_CTL_WB_ON_ITR_M BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)
#define PF_GLINT_DYN_CTL_INTENA_MSK_S 31
#define PF_GLINT_DYN_CTL_INTENA_MSK_M BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)
-#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start))
-#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is
+ * spacing b/w itrn registers of the same vector.
+ */
+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+ ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */
+#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))
#define PF_GLINT_ITR_MAX_INDEX 2
#define PF_GLINT_ITR_INTERVAL_S 0
#define PF_GLINT_ITR_INTERVAL_M MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)
diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h
index 9cd4f757d9..13c5c5a7da 100644
--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h
@@ -90,11 +90,18 @@
#define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)
#define VF_INT_DYN_CTLN_INTENA_MSK_S 31
#define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S)
-#define VF_INT_ITR0(_i) (0x00004C00 + ((_i) * 4))
-#define VF_INT_ITRN_V2(_i, _reg_start) ((_reg_start) + (((_i)) * 4))
-#define VF_INT_ITRN(_i, _INT) (0x00002800 + ((_i) * 4) + ((_INT) * 0x40))
-#define VF_INT_ITRN_64(_i, _INT) (0x00002C00 + ((_i) * 4) + ((_INT) * 0x100))
-#define VF_INT_ITRN_2K(_i, _INT) (0x00072000 + ((_i) * 4) + ((_INT) * 0x100))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing
+ * b/w itrn registers of the same vector
+ */
+#define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4))
+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+ ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */
+#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))
+/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */
+#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))
+/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */
+#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))
#define VF_INT_ITRN_MAX_INDEX 2
#define VF_INT_ITRN_INTERVAL_S 0
#define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)
--
2.25.1