From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0A4AA42A02; Wed, 26 Apr 2023 12:28:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9CE8042D46; Wed, 26 Apr 2023 12:28:08 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 3D50F42D3D for ; Wed, 26 Apr 2023 12:28:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682504884; x=1714040884; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GhO87oGG11ZM1yvafwTCi0+S6V7GZh/8I+81IGbEIfg=; b=kJRLRB2yGqTJOawhg8er9Ib6gz1z9jJhvtkPQFaOZ7aSU9uatAxE6O4G 6wZ7XQ9ek9S24YoCQzPrhoaOk4eNKEJuUoDVI5F+UEdZJtkpTeAnLPCm6 0Yej3iLdxvCY/j97vBFJeuV+kvy818pFck8ap4MnwprMiHdbTmRZxbq2K CqHojoIW7qgF7Qh87ZoqJALMu63IZxu0cXwQ1DuTKRLAo0LItaxoCmXqF 1lae0+1KwO5pFav3S0V7u69Ps0YgO7ndkpd7Pz6hXSrGLx3+afJi1s1tN YZFo2HWMCn68mUHr7eV/JaL1J960+i1nTCLjc6ncYfUg6zsXbqh2Cy5av g==; X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="327391517" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="327391517" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Apr 2023 03:28:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10691"; a="1023552695" X-IronPort-AV: E=Sophos;i="5.99,227,1677571200"; d="scan'208";a="1023552695" Received: from dpdk-wenjing-01.sh.intel.com ([10.67.118.239]) by fmsmga005.fm.intel.com with ESMTP; 26 Apr 2023 03:28:01 -0700 From: Wenjing Qiao To: jingjing.wu@intel.com, beilei.xing@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Wenjing Qiao , Pavan Kumar Linga Subject: [PATCH v3 06/15] common/idpf/base: modify SSO/LSO and ITR fields Date: Wed, 26 Apr 2023 06:22:50 -0400 Message-Id: <20230426102259.205992-7-wenjing.qiao@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230426102259.205992-1-wenjing.qiao@intel.com> References: <20230421084043.135503-2-wenjing.qiao@intel.com> <20230426102259.205992-1-wenjing.qiao@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org - Driver assumes minimum packet length for sso as 17 bytes but it should be a negotiated value from CP. - Similarly, the number of header buffers for lso that are supported by the device should also be a negotiated value. Add min_sso_packet_len, max_hdr_buf_per_lso to address the above. Also, the existing 'itrn_reg_spacing' should be used for spacing between ITRn registers of 2 consecutive vectors and add a new spacing field to get the spacing between ITR registers of the same vector. - ITR_IDX 2 is not used in the current code. Bring it back if there exists any use case in the future. - NO_ITR is not really a register index and it is used only in the IDPF base code, so virtchnl support is not required for that - itr_idx_map is also not used as by default driver assumes at the minimum 2 ITRs are supported by the device. If any additional ITRs are also supported, then those should be negotiated. Remove all the above said fields and mark them as reserved. Signed-off-by: Pavan Kumar Linga Signed-off-by: Wenjing Qiao --- drivers/common/idpf/base/virtchnl2.h | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/common/idpf/base/virtchnl2.h b/drivers/common/idpf/base/virtchnl2.h index 32d8fe8c06..edf3f200b3 100644 --- a/drivers/common/idpf/base/virtchnl2.h +++ b/drivers/common/idpf/base/virtchnl2.h @@ -289,8 +289,6 @@ */ #define VIRTCHNL2_ITR_IDX_0 0 #define VIRTCHNL2_ITR_IDX_1 1 -#define VIRTCHNL2_ITR_IDX_2 2 -#define VIRTCHNL2_ITR_IDX_NO_ITR 3 /* VIRTCHNL2_VECTOR_LIMITS * Since PF/VF messages are limited by __le16 size, precalculate the maximum @@ -510,9 +508,7 @@ struct virtchnl2_get_capabilities { */ u8 max_sg_bufs_per_tx_pkt; - /* see VIRTCHNL2_ITR_IDX definition */ - u8 itr_idx_map; - + u8 reserved1; __le16 pad1; /* version of Control Plane that is running */ @@ -521,7 +517,12 @@ struct virtchnl2_get_capabilities { /* see VIRTCHNL2_DEVICE_TYPE definitions */ __le32 device_type; - u8 reserved[12]; + /* min packet length supported by device for single segment offload */ + u8 min_sso_packet_len; + /* max number of header buffers that can be used for an LSO */ + u8 max_hdr_buf_per_lso; + + u8 reserved[10]; }; VIRTCHNL2_CHECK_STRUCT_LEN(80, virtchnl2_get_capabilities); @@ -789,15 +790,17 @@ struct virtchnl2_vector_chunk { * interrupt indices without modifying the state of the interrupt. */ __le32 dynctl_reg_start; - /* register spacing to find the next dynctl and itrn register offset - * from the provided dynctl_reg_start and itrn_reg_start respectively - */ + /* register spacing between dynctl registers of 2 consecutive vectors */ __le32 dynctl_reg_spacing; __le32 itrn_reg_start; - /* register spacing to find the individual itrn register where n=0..2 */ + /* register spacing between itrn registers of 2 consecutive vectors */ __le32 itrn_reg_spacing; - u8 reserved[8]; + /* register spacing between itrn registers of the same vector + * where n=0..2 + */ + __le32 itrn_index_spacing; + u8 reserved[4]; }; VIRTCHNL2_CHECK_STRUCT_LEN(32, virtchnl2_vector_chunk); -- 2.25.1