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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6363.20 via Frontend Transport; Tue, 2 May 2023 18:49:51 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 2 May 2023 11:49:38 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 2 May 2023 11:49:36 -0700 From: Alexander Kozyrev To: CC: , , , Subject: [PATCH] drivers: fix error CQE handling Date: Tue, 2 May 2023 21:49:22 +0300 Message-ID: <20230502184922.3249201-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT023:EE_|CH3PR12MB8282:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ba1f16d-ff67-4296-5589-08db4b3e02e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 May 2023 18:49:51.0330 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ba1f16d-ff67-4296-5589-08db4b3e02e8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8282 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The completion queue element size can be independently configured to report either 64 or 128 bytes CQEs by programming cqe_sz parameter at CQ creation. This parameter depends on the cache line size and affects both regular CQEs and error CQEs. But the error handling assumes that an error CQE is 64 bytes and doesn't take the padding into consideration on platforms with 128-byte cache lines. Fix the error CQE size in all error handling routines in mlx5. Fixes: 957e45fb7b ("net/mlx5: handle Tx completion with error") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev --- drivers/common/mlx5/mlx5_prm.h | 29 ++++++++++++++++++++- drivers/common/mlx5/windows/mlx5_win_defs.h | 12 --------- drivers/compress/mlx5/mlx5_compress.c | 4 +-- drivers/crypto/mlx5/mlx5_crypto.c | 2 +- drivers/net/mlx5/mlx5_flow_aso.c | 6 ++--- drivers/net/mlx5/mlx5_rx.c | 2 +- drivers/net/mlx5/mlx5_tx.c | 8 +++--- 7 files changed, 39 insertions(+), 24 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index ed3d5efbb7..505ff3cc8e 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -268,8 +268,12 @@ /* Maximum number of DS in WQE. Limited by 6-bit field. */ #define MLX5_DSEG_MAX 63 -/* The 32 bit syndrome offset in struct mlx5_err_cqe. */ +/* The 32 bit syndrome offset in struct mlx5_error_cqe. */ +#if (RTE_CACHE_LINE_SIZE == 128) +#define MLX5_ERROR_CQE_SYNDROME_OFFSET 116 +#else #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52 +#endif /* The completion mode offset in the WQE control segment line 2. */ #define MLX5_COMP_MODE_OFFSET 2 @@ -415,6 +419,29 @@ struct mlx5_wqe_mprq { #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2 +struct mlx5_error_cqe { +#if (RTE_CACHE_LINE_SIZE == 128) + uint8_t padding[64]; +#endif + uint8_t rsvd0[2]; + uint16_t eth_wqe_id; + uint8_t rsvd1[16]; + uint16_t ib_stride_index; + uint8_t rsvd2[10]; + uint32_t srqn; + uint8_t rsvd3[8]; + uint32_t byte_cnt; + uint8_t rsvd4[4]; + uint8_t hw_err_synd; + uint8_t hw_synd_type; + uint8_t vendor_err_synd; + uint8_t syndrome; + uint32_t s_wqe_opcode_qpn; + uint16_t wqe_counter; + uint8_t signature; + uint8_t op_own; +}; + /* CQ element structure - should be equal to the cache line size */ struct mlx5_cqe { #if (RTE_CACHE_LINE_SIZE == 128) diff --git a/drivers/common/mlx5/windows/mlx5_win_defs.h b/drivers/common/mlx5/windows/mlx5_win_defs.h index 65da820c5e..1ddf5c553d 100644 --- a/drivers/common/mlx5/windows/mlx5_win_defs.h +++ b/drivers/common/mlx5/windows/mlx5_win_defs.h @@ -219,18 +219,6 @@ struct mlx5_action { } dest_tir; }; -struct mlx5_err_cqe { - uint8_t rsvd0[32]; - uint32_t srqn; - uint8_t rsvd1[18]; - uint8_t vendor_err_synd; - uint8_t syndrome; - uint32_t s_wqe_opcode_qpn; - uint16_t wqe_counter; - uint8_t signature; - uint8_t op_own; -}; - struct mlx5_wqe_srq_next_seg { uint8_t rsvd0[2]; rte_be16_t next_wqe_index; diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 41d9752833..702108c5f9 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -602,7 +602,7 @@ mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe, size_t i; DRV_LOG(ERR, "Error cqe:"); - for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4) + for (i = 0; i < sizeof(struct mlx5_error_cqe) >> 2; i += 4) DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], cqe[i + 2], cqe[i + 3]); DRV_LOG(ERR, "\nError wqe:"); @@ -620,7 +620,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp, struct rte_comp_op *op) { const uint32_t idx = qp->ci & (qp->entries_n - 1); - volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) + volatile struct mlx5_error_cqe *cqe = (volatile struct mlx5_error_cqe *) &qp->cq.cqes[idx]; volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *) qp->qp.wqes; diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 5267f48c1e..ab2ffe6d7f 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -460,7 +460,7 @@ static __rte_noinline void mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op) { const uint32_t idx = qp->ci & (qp->entries_n - 1); - volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *) + volatile struct mlx5_error_cqe *cqe = (volatile struct mlx5_error_cqe *) &qp->cq_obj.cqes[idx]; op->status = RTE_CRYPTO_OP_STATUS_ERROR; diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c index 29bd7ce9e8..c2f9b2d507 100644 --- a/drivers/net/mlx5/mlx5_flow_aso.c +++ b/drivers/net/mlx5/mlx5_flow_aso.c @@ -489,7 +489,7 @@ mlx5_aso_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe) int i; DRV_LOG(ERR, "Error cqe:"); - for (i = 0; i < 16; i += 4) + for (i = 0; i < (int)sizeof(struct mlx5_error_cqe) / 4; i += 4) DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1], cqe[i + 2], cqe[i + 3]); DRV_LOG(ERR, "\nError wqe:"); @@ -509,8 +509,8 @@ mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq) { struct mlx5_aso_cq *cq = &sq->cq; uint32_t idx = cq->cq_ci & ((1 << cq->log_desc_n) - 1); - volatile struct mlx5_err_cqe *cqe = - (volatile struct mlx5_err_cqe *)&cq->cq_obj.cqes[idx]; + volatile struct mlx5_error_cqe *cqe = + (volatile struct mlx5_error_cqe *)&cq->cq_obj.cqes[idx]; cq->errors++; idx = rte_be_to_cpu_16(cqe->wqe_counter) & (1u << sq->log_desc_n); diff --git a/drivers/net/mlx5/mlx5_rx.c b/drivers/net/mlx5/mlx5_rx.c index a2be523e9e..69fd173239 100644 --- a/drivers/net/mlx5/mlx5_rx.c +++ b/drivers/net/mlx5/mlx5_rx.c @@ -459,7 +459,7 @@ mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec, container_of(rxq, struct mlx5_rxq_ctrl, rxq); union { volatile struct mlx5_cqe *cqe; - volatile struct mlx5_err_cqe *err_cqe; + volatile struct mlx5_error_cqe *err_cqe; } u = { .cqe = &(*rxq->cqes)[(rxq->cq_ci - vec) & cqe_mask], }; diff --git a/drivers/net/mlx5/mlx5_tx.c b/drivers/net/mlx5/mlx5_tx.c index 14e1487e59..8b1a0ca3d3 100644 --- a/drivers/net/mlx5/mlx5_tx.c +++ b/drivers/net/mlx5/mlx5_tx.c @@ -55,7 +55,7 @@ tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl) /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */ static int -check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe) +check_err_cqe_seen(volatile struct mlx5_error_cqe *err_cqe) { static const uint8_t magic[] = "seen"; int ret = 1; @@ -83,7 +83,7 @@ check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe) */ static int mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq, - volatile struct mlx5_err_cqe *err_cqe) + volatile struct mlx5_error_cqe *err_cqe) { if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) { const uint16_t wqe_m = ((1 << txq->wqe_n) - 1); @@ -107,7 +107,7 @@ mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq, mlx5_dump_debug_information(name, "MLX5 Error CQ:", (const void *)((uintptr_t) txq->cqes), - sizeof(struct mlx5_cqe) * + sizeof(struct mlx5_error_cqe) * (1 << txq->cqe_n)); mlx5_dump_debug_information(name, "MLX5 Error SQ:", (const void *)((uintptr_t) @@ -206,7 +206,7 @@ mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq, */ rte_wmb(); ret = mlx5_tx_error_cqe_handle - (txq, (volatile struct mlx5_err_cqe *)cqe); + (txq, (volatile struct mlx5_error_cqe *)cqe); if (unlikely(ret < 0)) { /* * Some error occurred on queue error -- 2.18.2