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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 May 2023 11:50:42.6033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a74e035c-42eb-4d4f-16fc-08db4bcc9fa9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7167 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org CQE Compression reduces PCI overhead by coalescing and compressing multiple CQEs into a single merged CQE. Add supported for the CQE compression feature on Windows. feature is enabled by default unless not supported by the HW or if the rxq_cqe_comp_en PMD argument is explicitly disabled. Signed-off-by: Tal Shnaiderman --- drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++ drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/net/mlx5/windows/mlx5_os.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 096bd1d520..a31e4995f5 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1062,6 +1062,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_flow_tag); + attr->cqe_compression_128 = MLX5_GET(cmd_hca_cap, hcattr, + cqe_compression_128); attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, mini_cqe_resp_l3_l4_tag); attr->enhanced_cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 9e7992b1c6..edcd867c4e 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -284,6 +284,7 @@ struct mlx5_hca_attr { uint16_t max_wqe_sz_sq; uint32_t striding_rq:1; uint32_t ext_stride_num_range:1; + uint32_t cqe_compression_128:1; uint32_t set_reg_c:8; uint32_t nic_flow_table:1; uint32_t modify_outer_ip_ecn:1; diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c index 0caa8931e4..6527269663 100644 --- a/drivers/net/mlx5/windows/mlx5_os.c +++ b/drivers/net/mlx5/windows/mlx5_os.c @@ -237,6 +237,18 @@ mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh) } else { DRV_LOG(DEBUG, "Tunnel offloading is not supported."); } + sh->dev_cap.cqe_comp = 0; +#if (RTE_CACHE_LINE_SIZE == 128) + if (hca_attr->cqe_compression_128) + sh->dev_cap.cqe_comp = 1; + DRV_LOG(DEBUG, "Rx CQE 128B compression is %ssupported.", + sh->dev_cap.cqe_comp ? "" : "not "); +#else + if (hca_attr->cqe_compression) + sh->dev_cap.cqe_comp = 1; + DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.", + sh->dev_cap.cqe_comp ? "" : "not "); +#endif snprintf(sh->dev_cap.fw_ver, 64, "%x.%x.%04x", MLX5_GET(initial_seg, pv_iseg, fw_rev_major), MLX5_GET(initial_seg, pv_iseg, fw_rev_minor), -- 2.16.1.windows.4