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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1NAM11FT088.mail.protection.outlook.com (10.13.175.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6411.15 via Frontend Transport; Tue, 16 May 2023 05:41:27 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Mon, 15 May 2023 22:41:12 -0700 Received: from nvidia.com (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Mon, 15 May 2023 22:41:10 -0700 From: Rongwei Liu To: , , , , CC: , Subject: [PATCH v1 2/2] net/mlx5: fix VXLAN matching with zero value Date: Tue, 16 May 2023 08:40:53 +0300 Message-ID: <20230516054053.1396711-3-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20230516054053.1396711-1-rongweil@nvidia.com> References: <20230516054053.1396711-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT088:EE_|IA1PR12MB6211:EE_ X-MS-Office365-Filtering-Correlation-Id: 04492973-db0b-4ea4-a980-08db55d03189 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 05:41:27.4627 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04492973-db0b-4ea4-a980-08db55d03189 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT088.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6211 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org When an application wants to match VxLAN last_rsvd value zero, PMD sets the matching mask field to zero by mistake and it causes traffic with any last_rsvd value hits. The matching mask should be taken from application input directly, no need to perform the bit reset operation. Fixes: cd4ab742064a ("net/mlx5: split flow item matcher and value translation") Cc: suanmingm@nvidia.com Cc: stable@dpdk.org Signed-off-by: Rongwei Liu Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_dv.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f44d621600..1abc4acad7 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -9480,12 +9480,10 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev, { const struct rte_flow_item_vxlan *vxlan_m; const struct rte_flow_item_vxlan *vxlan_v; - const struct rte_flow_item_vxlan *vxlan_vv = item->spec; void *headers_v; void *misc_v; void *misc5_v; uint32_t tunnel_v; - uint32_t *tunnel_header_v; char *vni_v; uint16_t dport; int size; @@ -9537,24 +9535,11 @@ flow_dv_translate_item_vxlan(struct rte_eth_dev *dev, vni_v[i] = vxlan_m->hdr.vni[i] & vxlan_v->hdr.vni[i]; return; } - tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5, - misc5_v, - tunnel_header_1); tunnel_v = (vxlan_v->hdr.vni[0] & vxlan_m->hdr.vni[0]) | (vxlan_v->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 8 | (vxlan_v->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 16; - *tunnel_header_v = tunnel_v; - if (key_type == MLX5_SET_MATCHER_SW_M) { - tunnel_v = (vxlan_vv->hdr.vni[0] & vxlan_m->hdr.vni[0]) | - (vxlan_vv->hdr.vni[1] & vxlan_m->hdr.vni[1]) << 8 | - (vxlan_vv->hdr.vni[2] & vxlan_m->hdr.vni[2]) << 16; - if (!tunnel_v) - *tunnel_header_v = 0x0; - if (vxlan_vv->hdr.rsvd1 & vxlan_m->hdr.rsvd1) - *tunnel_header_v |= vxlan_v->hdr.rsvd1 << 24; - } else { - *tunnel_header_v |= (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1) << 24; - } + tunnel_v |= (vxlan_v->hdr.rsvd1 & vxlan_m->hdr.rsvd1) << 24; + MLX5_SET(fte_match_set_misc5, misc5_v, tunnel_header_1, RTE_BE32(tunnel_v)); } /** -- 2.27.0