From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 60B8D42AF1; Thu, 18 May 2023 17:36:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 87E9142D8F; Thu, 18 May 2023 17:34:42 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 7C34F42D46 for ; Thu, 18 May 2023 17:34:40 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1684424080; x=1715960080; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WmOsaiQGrFn9mOCBYPB2lAsKq9TPGPsDoGMOTry00L8=; b=BFgH9fVNLBmkh+c+vAkLWn4afNUNNLsGRA2mY8ttWUTPq2RBDOo0S7Cp lyMnRvyB+GwvbzQu45BUA0//sPQPKJ0U5E7yK44rZbu+7WIkkM711Dqu5 3UHcs0gIoUqCTbFucwyLE0FDHhsBYYHFPmiT4U/rF9hxM+hbD9yWJQQD6 5m9P24f4bCWk9+DUV7tv8tRuXrj6tncsPICB8FgcVbo07UciAASHQN5mN OGY/4BQD6kDvMjLeXTgrnBOU909YIXvPgRvIPQJbwU9YyZoUw9hpdN2qb cgWjgBIkYAkywQ6lRFE2QCaefNPlkKwdPbZAJDhii8/X7leej0WQn32uP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="341527728" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="341527728" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 May 2023 08:34:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10714"; a="705235163" X-IronPort-AV: E=Sophos;i="5.99,285,1677571200"; d="scan'208";a="705235163" Received: from dpdk-qiming3.sh.intel.com ([10.67.111.4]) by fmsmga007.fm.intel.com with ESMTP; 18 May 2023 08:34:38 -0700 From: Qiming Yang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, Qiming Yang , Yahui Cao Subject: [PATCH v2 13/20] net/ice/base: add function to get rxq context Date: Thu, 18 May 2023 15:16:31 +0000 Message-Id: <20230518151638.1207021-14-qiming.yang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518151638.1207021-1-qiming.yang@intel.com> References: <20230427062001.478032-1-qiming.yang@intel.com> <20230518151638.1207021-1-qiming.yang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This patch exports rxq context which is consumed by linux live migration driver to save device state. Signed-off-by: Yahui Cao Signed-off-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 67 ++++++++++++++++++++++++++++--- drivers/net/ice/base/ice_common.h | 7 +++- 2 files changed, 67 insertions(+), 7 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index a958ecef83..9992d0ad4d 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -1381,6 +1381,37 @@ ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) return ICE_SUCCESS; } +/** + * ice_copy_rxq_ctx_from_hw - Copy rxq context register from HW + * @hw: pointer to the hardware structure + * @ice_rxq_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Copies rxq context from HW register space to dense structure + */ +static enum ice_status +ice_copy_rxq_ctx_from_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index) +{ + u8 i; + + if (!ice_rxq_ctx) + return ICE_ERR_BAD_PTR; + + if (rxq_index > QRX_CTRL_MAX_INDEX) + return ICE_ERR_PARAM; + + /* Copy each dword separately from HW */ + for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) { + u32 *ctx = (u32 *)(ice_rxq_ctx + (i * sizeof(u32))); + + *ctx = rd32(hw, QRX_CONTEXT(i, rxq_index)); + + ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i, *ctx); + } + + return ICE_SUCCESS; +} + /* LAN Rx Queue Context */ static const struct ice_ctx_ele ice_rlan_ctx_info[] = { /* Field Width LSB */ @@ -1432,6 +1463,32 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index); } +/** + * ice_read_rxq_ctx - Read rxq context from HW + * @hw: pointer to the hardware structure + * @rlan_ctx: pointer to the rxq context + * @rxq_index: the index of the Rx queue + * + * Read rxq context from HW register space and then converts it from dense + * structure to sparse + */ +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index) +{ + u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 }; + enum ice_status status; + + if (!rlan_ctx) + return ICE_ERR_BAD_PTR; + + status = ice_copy_rxq_ctx_from_hw(hw, ctx_buf, rxq_index); + if (status) + return status; + + return ice_get_ctx(ctx_buf, (u8 *)rlan_ctx, ice_rlan_ctx_info); +} + /** * ice_clear_rxq_ctx * @hw: pointer to the hardware structure @@ -4824,7 +4881,7 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, * @ce_info: a description of the struct to be filled */ static void -ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u8 dest_byte, mask; u8 *src, *target; @@ -4860,7 +4917,7 @@ ice_read_byte(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u16 dest_word, mask; u8 *src, *target; @@ -4903,7 +4960,7 @@ ice_read_word(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u32 dest_dword, mask; __le32 src_dword; @@ -4954,7 +5011,7 @@ ice_read_dword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the struct to be filled */ static void -ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_read_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { u64 dest_qword, mask; __le64 src_qword; @@ -5005,7 +5062,7 @@ ice_read_qword(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) * @ce_info: a description of the structure to be read from */ enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info) +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info) { int f; diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index e1febfb0c4..aff361e5aa 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -86,6 +86,9 @@ ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, enum ice_status ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, u32 rxq_index); +enum ice_status +ice_read_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx, + u32 rxq_index); enum ice_status ice_clear_rxq_ctx(struct ice_hw *hw, u32 rxq_index); enum ice_status ice_clear_tx_cmpltnq_ctx(struct ice_hw *hw, u32 tx_cmpltnq_index); @@ -128,6 +131,8 @@ extern const struct ice_ctx_ele ice_tlan_ctx_info[]; enum ice_status ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); +enum ice_status +ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info); enum ice_status ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, @@ -221,8 +226,6 @@ ice_aq_read_topo_dev_nvm(struct ice_hw *hw, u32 start_address, u8 *buf, u8 buf_size, struct ice_sq_cd *cd); -enum ice_status -ice_get_ctx(u8 *src_ctx, u8 *dest_ctx, struct ice_ctx_ele *ce_info); enum ice_status ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues, u16 *q_handle, u16 *q_ids, u32 *q_teids, -- 2.25.1