From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7BBF442B81; Tue, 23 May 2023 15:00:50 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BB7D40EF0; Tue, 23 May 2023 15:00:50 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 547D440689 for ; Tue, 23 May 2023 15:00:49 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34NCphmV025004 for ; Tue, 23 May 2023 06:00:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=QI98unYdbhipDydzq2qozSdhPiaWxqaTq3C61cEnRvM=; b=iMk1Ar5MQBf+ZuWfVEByC0VL9TzbwVYnw8so9ZvrmDZcCQxoBkogknkNT2Bb5od5pNQj EhF5sBfg9IbBGtQlovon+uX2+xyncfLP6wGIZwP6M2Y2bUsTZkYrmhb0jxCZbylOqx3d eiBeCsilf1YbBTHRLOzM4l/i3hhzymseRYHgQggNHzohTIru4ZDkFPKkpCNT9gjtgXJR 4lkQrq96rwrKS2dj9A4faEE7SlDcjHS+lK1qt8Vy6ltfgvjIsDYlPZpKN0+T6UmMa4EK NgLykJ27F3x9Z3yN1orlvJEs8CiPX2cQ+JonwK6GYEJdpbSSUW0jxHzSVC3Hd6yZNIjC jw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3qpwqk1e53-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 23 May 2023 06:00:48 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Tue, 23 May 2023 02:15:29 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Tue, 23 May 2023 02:15:29 -0700 Received: from localhost.localdomain (unknown [10.28.36.142]) by maili.marvell.com (Postfix) with ESMTP id CBE443F708A; Tue, 23 May 2023 02:15:25 -0700 (PDT) From: Ashwin Sekhar T K To: , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ashwin Sekhar T K , "Pavan Nikhilesh" CC: , , , , Subject: [PATCH v2 3/5] mempool/cnxk: add NPA aura range get/set APIs Date: Tue, 23 May 2023 14:43:58 +0530 Message-ID: <20230523091400.717834-3-asekhar@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230523091400.717834-1-asekhar@marvell.com> References: <20230411075528.1125799-1-asekhar@marvell.com> <20230523091400.717834-1-asekhar@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: sPZOy_FGYSFKu8QF4Gg4lIv_t6h_KJj9 X-Proofpoint-GUID: sPZOy_FGYSFKu8QF4Gg4lIv_t6h_KJj9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-23_08,2023-05-23_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Current APIs to set range on auras modifies both the aura range limits in software and pool range limits in NPA hardware. Newly added ROC APIs allow to set/get aura range limits in software alone without modifying hardware. The existing aura range set functionality has been moved as a pool range set API. Signed-off-by: Ashwin Sekhar T K --- drivers/common/cnxk/roc_nix_queue.c | 2 +- drivers/common/cnxk/roc_npa.c | 35 ++++++++++++++++++++++++- drivers/common/cnxk/roc_npa.h | 6 +++++ drivers/common/cnxk/roc_sso.c | 2 +- drivers/common/cnxk/version.map | 2 ++ drivers/mempool/cnxk/cnxk_mempool_ops.c | 2 +- 6 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c index 21bfe7d498..ac4d9856c1 100644 --- a/drivers/common/cnxk/roc_nix_queue.c +++ b/drivers/common/cnxk/roc_nix_queue.c @@ -1050,7 +1050,7 @@ sqb_pool_populate(struct roc_nix *roc_nix, struct roc_nix_sq *sq) goto npa_fail; } - roc_npa_aura_op_range_set(sq->aura_handle, (uint64_t)sq->sqe_mem, iova); + roc_npa_pool_op_range_set(sq->aura_handle, (uint64_t)sq->sqe_mem, iova); roc_npa_aura_limit_modify(sq->aura_handle, nb_sqb_bufs); sq->aura_sqb_bufs = nb_sqb_bufs; diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c index e3c925ddd1..3b0f95a304 100644 --- a/drivers/common/cnxk/roc_npa.c +++ b/drivers/common/cnxk/roc_npa.c @@ -18,7 +18,7 @@ roc_npa_lf_init_cb_register(roc_npa_lf_init_cb_t cb) } void -roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, +roc_npa_pool_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova) { const uint64_t start = roc_npa_aura_handle_to_base(aura_handle) + @@ -32,6 +32,7 @@ roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, PLT_ASSERT(lf); lim = lf->aura_lim; + /* Change the range bookkeeping in software as well as in hardware */ lim[reg].ptr_start = PLT_MIN(lim[reg].ptr_start, start_iova); lim[reg].ptr_end = PLT_MAX(lim[reg].ptr_end, end_iova); @@ -39,6 +40,38 @@ roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, roc_store_pair(lim[reg].ptr_end, reg, end); } +void +roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, + uint64_t end_iova) +{ + uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle); + struct npa_lf *lf = idev_npa_obj_get(); + struct npa_aura_lim *lim; + + PLT_ASSERT(lf); + lim = lf->aura_lim; + + /* Change only the bookkeeping in software */ + lim[reg].ptr_start = PLT_MIN(lim[reg].ptr_start, start_iova); + lim[reg].ptr_end = PLT_MAX(lim[reg].ptr_end, end_iova); +} + +void +roc_npa_aura_op_range_get(uint64_t aura_handle, uint64_t *start_iova, + uint64_t *end_iova) +{ + uint64_t aura_id = roc_npa_aura_handle_to_aura(aura_handle); + struct npa_aura_lim *lim; + struct npa_lf *lf; + + lf = idev_npa_obj_get(); + PLT_ASSERT(lf); + + lim = lf->aura_lim; + *start_iova = lim[aura_id].ptr_start; + *end_iova = lim[aura_id].ptr_end; +} + static int npa_aura_pool_init(struct mbox *m_box, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h index df15dabe92..21608a40d9 100644 --- a/drivers/common/cnxk/roc_npa.h +++ b/drivers/common/cnxk/roc_npa.h @@ -732,6 +732,12 @@ int __roc_api roc_npa_pool_range_update_check(uint64_t aura_handle); void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova); +void __roc_api roc_npa_aura_op_range_get(uint64_t aura_handle, + uint64_t *start_iova, + uint64_t *end_iova); +void __roc_api roc_npa_pool_op_range_set(uint64_t aura_handle, + uint64_t start_iova, + uint64_t end_iova); int __roc_api roc_npa_aura_create(uint64_t *aura_handle, uint32_t block_count, struct npa_aura_s *aura, int pool_id, uint32_t flags); diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c index 4a6a5080f7..c376bd837f 100644 --- a/drivers/common/cnxk/roc_sso.c +++ b/drivers/common/cnxk/roc_sso.c @@ -523,7 +523,7 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq, roc_npa_aura_op_free(xaq->aura_handle, 0, iova); iova += xaq_buf_size; } - roc_npa_aura_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova); + roc_npa_pool_op_range_set(xaq->aura_handle, (uint64_t)xaq->mem, iova); if (roc_npa_aura_op_available_wait(xaq->aura_handle, xaq->nb_xaq, 0) != xaq->nb_xaq) { diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 9414b55e9c..5281c71550 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -354,6 +354,7 @@ INTERNAL { roc_npa_buf_type_update; roc_npa_aura_drop_set; roc_npa_aura_limit_modify; + roc_npa_aura_op_range_get; roc_npa_aura_op_range_set; roc_npa_ctx_dump; roc_npa_dev_fini; @@ -365,6 +366,7 @@ INTERNAL { roc_npa_pool_create; roc_npa_pool_destroy; roc_npa_pool_op_pc_reset; + roc_npa_pool_op_range_set; roc_npa_pool_range_update_check; roc_npa_zero_aura_handle; roc_npc_fini; diff --git a/drivers/mempool/cnxk/cnxk_mempool_ops.c b/drivers/mempool/cnxk/cnxk_mempool_ops.c index 1b6c4591bb..a1aeaee746 100644 --- a/drivers/mempool/cnxk/cnxk_mempool_ops.c +++ b/drivers/mempool/cnxk/cnxk_mempool_ops.c @@ -174,7 +174,7 @@ cnxk_mempool_populate(struct rte_mempool *mp, unsigned int max_objs, plt_npa_dbg("requested objects %" PRIu64 ", possible objects %" PRIu64 "", (uint64_t)max_objs, (uint64_t)num_elts); - roc_npa_aura_op_range_set(mp->pool_id, iova, + roc_npa_pool_op_range_set(mp->pool_id, iova, iova + num_elts * total_elt_sz); if (roc_npa_pool_range_update_check(mp->pool_id) < 0) -- 2.25.1