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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN8NAM11FT091.mail.protection.outlook.com (10.13.176.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6433.18 via Frontend Transport; Fri, 26 May 2023 03:15:36 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Thu, 25 May 2023 20:15:19 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 25 May 2023 20:15:17 -0700 From: Suanming Mou <suanmingm@nvidia.com> To: CC: <dev@dpdk.org>, <rasland@nvidia.com> Subject: [PATCH v2 0/9] crypto/mlx5: support AES-GCM Date: Fri, 26 May 2023 06:14:12 +0300 Message-ID: <20230526031422.913377-1-suanmingm@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230418092325.2578712-1-suanmingm@nvidia.com> References: <20230418092325.2578712-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT091:EE_|CH3PR12MB8185:EE_ X-MS-Office365-Filtering-Correlation-Id: 17500a27-a035-4980-393b-08db5d9779e0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 May 2023 03:15:36.7364 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17500a27-a035-4980-393b-08db5d9779e0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT091.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8185 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org AES-GCM provides both authenticated encryption and the ability to check the integrity and authentication of additional authenticated data (AAD) that is sent in the clear. The crypto operations are performed with crypto WQE. If the input buffers(AAD, mbuf, digest) are not contiguous and there is no enough headroom or tailroom for AAD or digest, as the requirement from FW, an UMR WQE is needed to generate contiguous address space for crypto WQE. The UMR WQE and crypto WQE are handled in two different QPs. The QP for UMR operation contains two types of WQE, UMR and SEND_EN WQE. The WQEs are built dynamically according to the crypto operation buffer address. Crypto operation with non-contiguous buffers will have its own UMR WQE, while the operation with contiguous buffers doesn't need the UMR WQE. Once the all the operations WQE in the enqueue burst built finishes, if any UMR WQEs are built, additional SEND_EN WQE will be as the final WQE of the burst in the UMR QP. The purpose of that SEND_EN WQE is to trigger the crypto QP processing with the UMR ready input memory address space buffers. The QP for crypto operations contains only the crypto WQE and the QP WQEs are built as fixed in QP setup. The QP processing is triggered by doorbell ring or the SEND_EN WQE from UMR QP. Suanming Mou (9): common/mlx5: export memory region lookup by address crypto/mlx5: split AES-XTS crypto/mlx5: add AES-GCM query and initialization crypto/mlx5: add AES-GCM encryption key crypto/mlx5: add AES-GCM session configure common/mlx5: add WQE-based QP synchronous basics crypto/mlx5: add queue pair setup for GCM crypto/mlx5: add enqueue and dequeue operations crypto/mlx5: enable AES-GCM capability doc/guides/cryptodevs/mlx5.rst | 48 +- doc/guides/rel_notes/release_23_07.rst | 1 + drivers/common/mlx5/mlx5_common_mr.c | 2 +- drivers/common/mlx5/mlx5_common_mr.h | 5 + drivers/common/mlx5/mlx5_devx_cmds.c | 21 + drivers/common/mlx5/mlx5_devx_cmds.h | 16 + drivers/common/mlx5/mlx5_prm.h | 65 +- drivers/common/mlx5/version.map | 3 + drivers/crypto/mlx5/meson.build | 2 + drivers/crypto/mlx5/mlx5_crypto.c | 673 ++--------------- drivers/crypto/mlx5/mlx5_crypto.h | 101 ++- drivers/crypto/mlx5/mlx5_crypto_dek.c | 102 ++- drivers/crypto/mlx5/mlx5_crypto_gcm.c | 995 +++++++++++++++++++++++++ drivers/crypto/mlx5/mlx5_crypto_xts.c | 645 ++++++++++++++++ 14 files changed, 2014 insertions(+), 665 deletions(-) create mode 100644 drivers/crypto/mlx5/mlx5_crypto_gcm.c create mode 100644 drivers/crypto/mlx5/mlx5_crypto_xts.c -- 2.25.1