From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3E0D142BF0; Wed, 31 May 2023 12:43:44 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 04F7E42D32; Wed, 31 May 2023 12:43:26 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 659DC42D20 for ; Wed, 31 May 2023 12:43:21 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685529801; x=1717065801; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0J3kCWXQyej1pfHQj5Q0eZprYBPaCR3/PoNyi/pb6ZU=; b=JF/5OyRT9AfpNhA4bFukE6N1+Uk5irHv1B9Q0qpmEehUQ2QjDtBFVQ2+ ujsUtOLGeL9SL5mpA2rI4OAaFLPWZNUecPBs3jSrZJKUxNR0BBHTUxTzP hX4VBSgSt1pnnPGTkrOMCV4hhjTAQNy23ocbdCvfvVkL5Tt9kpNdmAVbw I4tvgw50NBKT/OtCHTCc8tu4HsmYeZWdRqnTL2ZA01AM0+STJNB1CRZxJ mWZTapQje7aqQE0VPQztS/YUt1jZb4TWpso6voOvgWHT1JKuUtajad9iw KEInlzi3Daw3u2RuEdDJNgLsSu1FJxxDgEcXBDzIYMIQdL44DNY03P+Ig w==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="354044999" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="354044999" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2023 03:43:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="881129634" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="881129634" Received: from dpdk-beileix-3.sh.intel.com ([10.67.110.253]) by orsmga005.jf.intel.com with ESMTP; 31 May 2023 03:43:19 -0700 From: beilei.xing@intel.com To: jingjing.wu@intel.com Cc: dev@dpdk.org, mingxia.liu@intel.com, Beilei Xing , Xiao Wang Subject: [PATCH v5 04/13] net/cpfl: support hairpin queue capbility get Date: Wed, 31 May 2023 10:18:44 +0000 Message-Id: <20230531101853.20468-5-beilei.xing@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20230531101853.20468-1-beilei.xing@intel.com> References: <20230526073850.101079-1-beilei.xing@intel.com> <20230531101853.20468-1-beilei.xing@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Beilei Xing This patch adds hairpin_cap_get ops support. Signed-off-by: Xiao Wang Signed-off-by: Mingxia Liu Signed-off-by: Beilei Xing --- drivers/net/cpfl/cpfl_ethdev.c | 18 ++++++++++++++++++ drivers/net/cpfl/cpfl_rxtx.h | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c index c1273a7478..40b4515539 100644 --- a/drivers/net/cpfl/cpfl_ethdev.c +++ b/drivers/net/cpfl/cpfl_ethdev.c @@ -154,6 +154,23 @@ cpfl_dev_link_update(struct rte_eth_dev *dev, return rte_eth_linkstatus_set(dev, &new_link); } +static int +cpfl_hairpin_cap_get(struct rte_eth_dev *dev, + struct rte_eth_hairpin_cap *cap) +{ + struct cpfl_vport *cpfl_vport = dev->data->dev_private; + + if (cpfl_vport->p2p_q_chunks_info == NULL) + return -ENOTSUP; + + cap->max_nb_queues = CPFL_MAX_P2P_NB_QUEUES; + cap->max_rx_2_tx = CPFL_MAX_HAIRPINQ_RX_2_TX; + cap->max_tx_2_rx = CPFL_MAX_HAIRPINQ_TX_2_RX; + cap->max_nb_desc = CPFL_MAX_HAIRPINQ_NB_DESC; + + return 0; +} + static int cpfl_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) { @@ -904,6 +921,7 @@ static const struct eth_dev_ops cpfl_eth_dev_ops = { .xstats_get = cpfl_dev_xstats_get, .xstats_get_names = cpfl_dev_xstats_get_names, .xstats_reset = cpfl_dev_xstats_reset, + .hairpin_cap_get = cpfl_hairpin_cap_get, }; static int diff --git a/drivers/net/cpfl/cpfl_rxtx.h b/drivers/net/cpfl/cpfl_rxtx.h index 1fe65778f0..a4a164d462 100644 --- a/drivers/net/cpfl/cpfl_rxtx.h +++ b/drivers/net/cpfl/cpfl_rxtx.h @@ -14,6 +14,9 @@ #define CPFL_MAX_RING_DESC 4096 #define CPFL_DMA_MEM_ALIGN 4096 +#define CPFL_MAX_HAIRPINQ_RX_2_TX 1 +#define CPFL_MAX_HAIRPINQ_TX_2_RX 1 +#define CPFL_MAX_HAIRPINQ_NB_DESC 1024 #define CPFL_MAX_P2P_NB_QUEUES 16 #define CPFL_P2P_NB_RX_BUFQ 1 #define CPFL_P2P_NB_TX_COMPLQ 1 -- 2.26.2