From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 65CBE42BF8; Wed, 31 May 2023 20:43:46 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00C1140A89; Wed, 31 May 2023 20:43:46 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2053.outbound.protection.outlook.com [40.107.100.53]) by mails.dpdk.org (Postfix) with ESMTP id 4951F40A82; Wed, 31 May 2023 20:43:44 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f3YqCftWl6G05OEuE8xbr94IHBRwaIUFj4EM0HLgBpJ2EOYkVwNGFOS+UwjQg/ZrkrLLZhv51+yhgLjTJ2c/bX13wyV9jeqEiM9QGrSSXoaaJS7dqyquO9DNSmD9qEKT2DFytwXM97bF571kIpK53j7OOa4O3sAGgnykCfRBdf+k2BljxT3etl/HVqYHm+0g+G0XFe5qL/biYfnaSbQXsOQS5fLTSVi3asbU0Fv89bRfFKs8ijW8Uj/4aWmUBe0Ad+ub71sfClzsOGleiubGbwqvgtkuR+LmVVc1BooqIzldo5XG/wwRymuO1Kc7qDjYmGINQsmhhfCgT2IlKbuuTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zhd61qCw/WsXOTCuKpMa6F7gv24Fk1fT++tf3eQOxI0=; b=OENpvHJgAKyR3Q5UNyEiJzE01chWrJsfOMAjV0VE2WQM803HpguJje1izWBJXg8IUXHDcBH05PFxXXJO+vfEkv4k73A+zbb+9cIm5L6+ABip8B/5Fa9bZVifrA15BWlMQyQdSTH/k8kyjS4HwToOH06W5gbgQ7HbaNAmcXo3JMFTjh8XXSty8njAx4morqaec9c7Kpog6oBpEgkacbA6v8XfWFKbU5ys2v+vPM4hWfDkHKMPlB4lG2u/WSskpiUKW2VdnOMArWeYN0lppFY8QowIlFxoHpQDjWZdvOpCBaCJSetS3zQI6abz4cOhFOf+RsERzQmuDw2oQLZaGlDD+A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zhd61qCw/WsXOTCuKpMa6F7gv24Fk1fT++tf3eQOxI0=; b=lNX76kskMsqAnZNahVVGye9pMD8PjidxvnA/9En8ObFhaYPeMqDieDiCDPfp/dSR4cRio9xYhsbYUmhUCqyz8WIfutHnb4qLd5as8hr6mL+ZwnGnr9zEZGLcwyih0vRinolGZBAcL0EhBx7M22KVKDRhAz7tZzyHCSBU69FVkAR8l9mCrI/1Fl1L7TXYfsVnd9VQsMRFPxynKKCbvUXQkwvJAfyHkjfWFebEGwcFQSmTk1s2HFUL6L9I+/7HSP1MAYLYl5cEhAImF+9SBX9/0xPj2bbPkOvSF4OGbZLvALHQTfwdEre2jkrqKvPS2xd76xbwbK/5Uhk4uK6P8LLq3Q== Received: from DM6PR17CA0022.namprd17.prod.outlook.com (2603:10b6:5:1b3::35) by PH8PR12MB7253.namprd12.prod.outlook.com (2603:10b6:510:226::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.22; Wed, 31 May 2023 18:43:42 +0000 Received: from DM6NAM11FT107.eop-nam11.prod.protection.outlook.com (2603:10b6:5:1b3:cafe::1b) by DM6PR17CA0022.outlook.office365.com (2603:10b6:5:1b3::35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.22 via Frontend Transport; Wed, 31 May 2023 18:43:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT107.mail.protection.outlook.com (10.13.172.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6455.23 via Frontend Transport; Wed, 31 May 2023 18:43:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Wed, 31 May 2023 11:43:27 -0700 Received: from pegasus01.mtr.labs.mlnx (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 31 May 2023 11:43:24 -0700 From: Alexander Kozyrev To: CC: , , , , Subject: [PATCH] net/mlx5: fix MPRQ stride size to accommodate the headroom Date: Wed, 31 May 2023 21:43:03 +0300 Message-ID: <20230531184303.946971-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT107:EE_|PH8PR12MB7253:EE_ X-MS-Office365-Filtering-Correlation-Id: 91803b0d-a5b0-4f5a-f7b2-08db6206f4d2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /3wfUgg/DFi2WQw/hYCuwOwcXhCLhRNc9pcmZzGRzAUFKaKAkbvjVyfPAHk5UdHTqhu/1asWf94NCGrWX5Su5KtoMxMFaBIGcwAvuTq4mTs00W1gApKmz0KdVvMbPoP7mdRoSN5Tqg9aR2ymaeVuvjXs5WKTlDDT2sH8iNCHCpopDIOnlzIPySVB5Tv7bEFL/OPAsL827UYTdpqxI7Jmpbw+AurK1VPEiPTBGXz9j9t5MlPxmZTuB46wK6bhJeHAFtOLROf2roW5PViHm5TSgL/zZk4WtuLDxWelS2mSljbeoeC4y5YchOlpkKTzJYUbhG9z+wP3STF2DOdMeigvmykkL57SmDOHhfIOrLrU0HnfZyg9KltkpxxtFGH+d5YpsUKMmds/1RoCBbgb/LL/e/sgkSV5W3713w7AZjTnysqbg3f+yOOHn7gAilfxy2PFWQ34eyeT/J+pf+uUC66P6KUMCsggus9kpENC3Xhmc9brDT1b0s42PHdGXcbV8aNJsoV0+IDkngwE3kd/IVltZPABgT4XUzn5vOYKtXPtgWfVqrJRudXxOEMs6M0eychRbbjauvboFZXx8m2iPCU2XWOs7/ATMQ+1ES2AavTmZsDbc4IuujjKWSOGJWekpi9+zU+F5lo62eb5eHjwt0+zZW6P11/GtD4wSzmDo1093vl35y4lr+g33NrHhJeVEI9zffK0wazQ7piAOdktQRGEgajYIKEmMdBEec9LDlv2tZ+sM3ejd/EYrvREytNFUyMV X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(376002)(39860400002)(396003)(346002)(136003)(451199021)(46966006)(36840700001)(40470700004)(82310400005)(316002)(356005)(7636003)(1076003)(186003)(16526019)(82740400003)(40480700001)(8676002)(8936002)(41300700001)(107886003)(40460700003)(6666004)(5660300002)(26005)(47076005)(36756003)(83380400001)(36860700001)(4326008)(2906002)(6916009)(70206006)(70586007)(54906003)(2616005)(86362001)(336012)(450100002)(478600001)(426003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2023 18:43:41.8443 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 91803b0d-a5b0-4f5a-f7b2-08db6206f4d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7253 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The space for the headroom is reserved at the end of every MPRQ stride for the next packet. The Rx burst logic is to copy any overlapping packet data if there is an overlap with this reserved headroom space. But it is not possible if the headroom size is bigger than the whole stride. Adjust the stride size to make sure the stride size is greater than the headroom size. Fixes: 34776af600df ("net/mlx5: fix MPRQ stride devargs adjustment") Signed-off-by: Alexander Kozyrev --- drivers/net/mlx5/mlx5.c | 1 + drivers/net/mlx5/mlx5_rxq.c | 41 +++++++++++++++++++++++++------------ 2 files changed, 29 insertions(+), 13 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index a75fa1b7f0..592e4053c5 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -2597,6 +2597,7 @@ mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; + config->mprq.log_stride_size = MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE; config->log_hp_size = MLX5_ARG_UNSET; config->std_delay_drop = 0; config->hp_delay_drop = 0; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index ad8fd13cbe..da31b9a106 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -1604,23 +1604,38 @@ mlx5_mprq_prepare(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, } else { *actual_log_stride_num = config->mprq.log_stride_num; } - if (config->mprq.log_stride_size) { - /* Checks if chosen size of stride is in supported range. */ - if (config->mprq.log_stride_size > log_max_stride_size || - config->mprq.log_stride_size < log_min_stride_size) { - *actual_log_stride_size = log_def_stride_size; + /* Checks if chosen size of stride is in supported range. */ + if (config->mprq.log_stride_size > log_max_stride_size || + config->mprq.log_stride_size < log_min_stride_size) { + *actual_log_stride_size = log_def_stride_size; + DRV_LOG(WARNING, + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)", + dev->data->port_id, idx, + RTE_BIT32(log_def_stride_size)); + } else { + *actual_log_stride_size = config->mprq.log_stride_size; + } + /* Make the stride fit the mbuf size by default. */ + if (*actual_log_stride_size == MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE) { + if (min_mbuf_size <= RTE_BIT32(log_max_stride_size)) { DRV_LOG(WARNING, - "Port %u Rx queue %u size of a stride for Multi-Packet RQ is out of range, setting default value (%u)", - dev->data->port_id, idx, - RTE_BIT32(log_def_stride_size)); + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to match the mbuf size (%u)", + dev->data->port_id, idx, min_mbuf_size); + *actual_log_stride_size = log2above(min_mbuf_size); } else { - *actual_log_stride_size = config->mprq.log_stride_size; + goto unsupport; } - } else { - if (min_mbuf_size <= RTE_BIT32(log_max_stride_size)) - *actual_log_stride_size = log2above(min_mbuf_size); - else + } + /* Make sure the stride size is greater than the headroom. */ + if (RTE_BIT32(*actual_log_stride_size) < RTE_PKTMBUF_HEADROOM) { + if (RTE_BIT32(log_max_stride_size) > RTE_PKTMBUF_HEADROOM) { + DRV_LOG(WARNING, + "Port %u Rx queue %u size of a stride for Multi-Packet RQ is adjusted to accomodate the headroom (%u)", + dev->data->port_id, idx, RTE_PKTMBUF_HEADROOM); + *actual_log_stride_size = log2above(RTE_PKTMBUF_HEADROOM); + } else { goto unsupport; + } } log_stride_wqe_size = *actual_log_stride_num + *actual_log_stride_size; /* Check if WQE buffer size is supported by hardware. */ -- 2.18.2