From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 53CAF42C4E; Wed, 7 Jun 2023 17:28:39 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 76D2742C4D; Wed, 7 Jun 2023 17:28:35 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4E1A941149 for ; Wed, 7 Jun 2023 17:28:33 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 357Dvh1n028122; Wed, 7 Jun 2023 08:28:32 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=gHP4iRk11xbbzV0BPqN2egs1bV2C9463G8IoxkRIZpI=; b=WGyhlzZOoaK6HGUBserfgdbwRmw8N5/Fn2jdjFZq9lt5d1Foiv//dGrYeIjV/wOuehQN ncc/zqCTNwtFncEH0fPNbTb3nkHL80rENTF7vymbJBuhSdGUvspmZDrSVOUP+/0+7aA5 NZyTm9fJRKVW4gfm1AAtFhEn1lEqXVAZHyDKtAIqf+yjCV001p+NAq6EBTE4lTYyzMUk DcC6cNXcmhe2RDUEpLrUxf/ZieSHMktg9cZ7cHVhQivL4qLtJW/M7cjU8cOy5sKS+xUY x72qnLSl+DHCWaSa3XuWU3jsO+nVxZCx3+GtAwsPA5GewVaN3b6N1Cuu9G0Wzm2p6ifG xQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3r2a7bv7t4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 07 Jun 2023 08:28:32 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 7 Jun 2023 08:28:30 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Jun 2023 08:28:30 -0700 Received: from localhost.localdomain (unknown [10.28.36.102]) by maili.marvell.com (Postfix) with ESMTP id DF1703F7084; Wed, 7 Jun 2023 08:28:27 -0700 (PDT) From: Akhil Goyal To: CC: , , , , , , Akhil Goyal Subject: [PATCH v2 02/15] common/cnxk: add MACsec SA configuration Date: Wed, 7 Jun 2023 20:58:06 +0530 Message-ID: <20230607152819.226838-3-gakhil@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230607152819.226838-1-gakhil@marvell.com> References: <20230523200401.1945974-1-gakhil@marvell.com> <20230607152819.226838-1-gakhil@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: teQnRqAxXcLFSevWcK-7m_od9mcbMsF8 X-Proofpoint-GUID: teQnRqAxXcLFSevWcK-7m_od9mcbMsF8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-07_07,2023-06-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Added ROC APIs to allocate/free MACsec resources and APIs to write SA policy. Signed-off-by: Ankur Dwivedi Signed-off-by: Vamsi Attunuru Signed-off-by: Akhil Goyal --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_mbox.h | 12 ++ drivers/common/cnxk/roc_mcs.h | 43 ++++++ drivers/common/cnxk/roc_mcs_sec_cfg.c | 211 ++++++++++++++++++++++++++ drivers/common/cnxk/version.map | 4 + 5 files changed, 271 insertions(+) create mode 100644 drivers/common/cnxk/roc_mcs_sec_cfg.c diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index e33c002676..589baf74fe 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -27,6 +27,7 @@ sources = files( 'roc_ie_ot.c', 'roc_mbox.c', 'roc_mcs.c', + 'roc_mcs_sec_cfg.c', 'roc_ml.c', 'roc_model.c', 'roc_nix.c', diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index ef7a7d6513..ab1173e805 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -300,6 +300,7 @@ struct mbox_msghdr { M(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req, \ mcs_alloc_rsrc_rsp) \ M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \ + M(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, mcs_sa_plcy_write_req, msg_rsp) \ M(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \ /* Messages initiated by AF (range 0xC00 - 0xDFF) */ @@ -725,6 +726,17 @@ struct mcs_free_rsrc_req { uint64_t __io rsvd; }; +struct mcs_sa_plcy_write_req { + struct mbox_msghdr hdr; + uint64_t __io plcy[2][9]; /* Support 2 SA policy */ + uint8_t __io sa_index[2]; + uint8_t __io sa_cnt; + uint8_t __io mcs_id; + uint8_t __io dir; + uint64_t __io rsvd; +}; + + struct mcs_hw_info { struct mbox_msghdr hdr; uint8_t __io num_mcs_blks; /* Number of MCS blocks */ diff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h index 2f06ce2659..ea4c6ddc05 100644 --- a/drivers/common/cnxk/roc_mcs.h +++ b/drivers/common/cnxk/roc_mcs.h @@ -7,6 +7,39 @@ #define MCS_AES_GCM_256_KEYLEN 32 +struct roc_mcs_alloc_rsrc_req { + uint8_t rsrc_type; + uint8_t rsrc_cnt; /* Resources count */ + uint8_t dir; /* Macsec ingress or egress side */ + uint8_t all; /* Allocate all resource type one each */ +}; + +struct roc_mcs_alloc_rsrc_rsp { + uint8_t flow_ids[128]; /* Index of reserved entries */ + uint8_t secy_ids[128]; + uint8_t sc_ids[128]; + uint8_t sa_ids[256]; + uint8_t rsrc_type; + uint8_t rsrc_cnt; /* No of entries reserved */ + uint8_t dir; + uint8_t all; +}; + +struct roc_mcs_free_rsrc_req { + uint8_t rsrc_id; /* Index of the entry to be freed */ + uint8_t rsrc_type; + uint8_t dir; + uint8_t all; /* Free all the cam resources */ +}; + + +struct roc_mcs_sa_plcy_write_req { + uint64_t plcy[2][9]; + uint8_t sa_index[2]; + uint8_t sa_cnt; + uint8_t dir; +}; + struct roc_mcs_hw_info { uint8_t num_mcs_blks; /* Number of MCS blocks */ uint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */ @@ -38,4 +71,14 @@ __roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs); __roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx); /* HW info get */ __roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info); + +/* Resource allocation and free */ +__roc_api int roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, + struct roc_mcs_alloc_rsrc_rsp *rsp); +__roc_api int roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req); +/* SA policy read and write */ +__roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs, + struct roc_mcs_sa_plcy_write_req *sa_plcy); +__roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs, + struct roc_mcs_sa_plcy_write_req *sa_plcy); #endif /* _ROC_MCS_H_ */ diff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c new file mode 100644 index 0000000000..041be51b4b --- /dev/null +++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2023 Marvell. + */ + +#include "roc_api.h" +#include "roc_priv.h" + +int +roc_mcs_rsrc_alloc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req, + struct roc_mcs_alloc_rsrc_rsp *rsp) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_alloc_rsrc_req *rsrc_req; + struct mcs_alloc_rsrc_rsp *rsrc_rsp; + int rc, i; + + MCS_SUPPORT_CHECK; + + if (req == NULL || rsp == NULL) + return -EINVAL; + + rsrc_req = mbox_alloc_msg_mcs_alloc_resources(mcs->mbox); + if (rsrc_req == NULL) + return -ENOMEM; + + rsrc_req->rsrc_type = req->rsrc_type; + rsrc_req->rsrc_cnt = req->rsrc_cnt; + rsrc_req->mcs_id = mcs->idx; + rsrc_req->dir = req->dir; + rsrc_req->all = req->all; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsrc_rsp); + if (rc) + return rc; + + if (rsrc_rsp->all) { + rsrc_rsp->rsrc_cnt = 1; + rsrc_rsp->rsrc_type = 0xFF; + } + + for (i = 0; i < rsrc_rsp->rsrc_cnt; i++) { + switch (rsrc_rsp->rsrc_type) { + case MCS_RSRC_TYPE_FLOWID: + rsp->flow_ids[i] = rsrc_rsp->flow_ids[i]; + plt_bitmap_set(priv->dev_rsrc.tcam_bmap, + rsp->flow_ids[i] + + ((req->dir == MCS_TX) ? priv->tcam_entries : 0)); + break; + case MCS_RSRC_TYPE_SECY: + rsp->secy_ids[i] = rsrc_rsp->secy_ids[i]; + plt_bitmap_set(priv->dev_rsrc.secy_bmap, + rsp->secy_ids[i] + + ((req->dir == MCS_TX) ? priv->secy_entries : 0)); + break; + case MCS_RSRC_TYPE_SC: + rsp->sc_ids[i] = rsrc_rsp->sc_ids[i]; + plt_bitmap_set(priv->dev_rsrc.sc_bmap, + rsp->sc_ids[i] + + ((req->dir == MCS_TX) ? priv->sc_entries : 0)); + break; + case MCS_RSRC_TYPE_SA: + rsp->sa_ids[i] = rsrc_rsp->sa_ids[i]; + plt_bitmap_set(priv->dev_rsrc.sa_bmap, + rsp->sa_ids[i] + + ((req->dir == MCS_TX) ? priv->sa_entries : 0)); + break; + default: + rsp->flow_ids[i] = rsrc_rsp->flow_ids[i]; + rsp->secy_ids[i] = rsrc_rsp->secy_ids[i]; + rsp->sc_ids[i] = rsrc_rsp->sc_ids[i]; + rsp->sa_ids[i] = rsrc_rsp->sa_ids[i]; + plt_bitmap_set(priv->dev_rsrc.tcam_bmap, + rsp->flow_ids[i] + + ((req->dir == MCS_TX) ? priv->tcam_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.secy_bmap, + rsp->secy_ids[i] + + ((req->dir == MCS_TX) ? priv->secy_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.sc_bmap, + rsp->sc_ids[i] + + ((req->dir == MCS_TX) ? priv->sc_entries : 0)); + plt_bitmap_set(priv->dev_rsrc.sa_bmap, + rsp->sa_ids[i] + + ((req->dir == MCS_TX) ? priv->sa_entries : 0)); + break; + } + } + rsp->rsrc_type = rsrc_rsp->rsrc_type; + rsp->rsrc_cnt = rsrc_rsp->rsrc_cnt; + rsp->dir = rsrc_rsp->dir; + rsp->all = rsrc_rsp->all; + + return 0; +} + +int +roc_mcs_rsrc_free(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *free_req) +{ + struct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs); + struct mcs_free_rsrc_req *req; + struct msg_rsp *rsp; + uint32_t pos; + int i, rc; + + MCS_SUPPORT_CHECK; + + if (free_req == NULL) + return -EINVAL; + + req = mbox_alloc_msg_mcs_free_resources(mcs->mbox); + if (req == NULL) + return -ENOMEM; + + req->rsrc_id = free_req->rsrc_id; + req->rsrc_type = free_req->rsrc_type; + req->mcs_id = mcs->idx; + req->dir = free_req->dir; + req->all = free_req->all; + + rc = mbox_process_msg(mcs->mbox, (void *)&rsp); + if (rc) + return rc; + + switch (free_req->rsrc_type) { + case MCS_RSRC_TYPE_FLOWID: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->tcam_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.tcam_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].tcam_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].tcam_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SECY: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->secy_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.secy_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].secy_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].secy_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SC: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sc_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.sc_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sc_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].sc_bmap, pos); + break; + } + } + break; + case MCS_RSRC_TYPE_SA: + pos = free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sa_entries : 0); + plt_bitmap_clear(priv->dev_rsrc.sa_bmap, pos); + for (i = 0; i < MAX_PORTS_PER_MCS; i++) { + uint32_t set = plt_bitmap_get(priv->port_rsrc[i].sa_bmap, pos); + + if (set) { + plt_bitmap_clear(priv->port_rsrc[i].sa_bmap, pos); + break; + } + } + break; + default: + break; + } + + return rc; +} + +int +roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy) +{ + struct mcs_sa_plcy_write_req *sa; + struct msg_rsp *rsp; + + MCS_SUPPORT_CHECK; + + if (sa_plcy == NULL) + return -EINVAL; + + sa = mbox_alloc_msg_mcs_sa_plcy_write(mcs->mbox); + if (sa == NULL) + return -ENOMEM; + + mbox_memcpy(sa->plcy, sa_plcy->plcy, sizeof(uint64_t) * 2 * 9); + sa->sa_index[0] = sa_plcy->sa_index[0]; + sa->sa_index[1] = sa_plcy->sa_index[1]; + sa->sa_cnt = sa_plcy->sa_cnt; + sa->mcs_id = mcs->idx; + sa->dir = sa_plcy->dir; + + return mbox_process_msg(mcs->mbox, (void *)&rsp); +} + +int +roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused, + struct roc_mcs_sa_plcy_write_req *sa __plt_unused) +{ + MCS_SUPPORT_CHECK; + + return -ENOTSUP; +} diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 900290b866..bd8a3095f9 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -139,6 +139,10 @@ INTERNAL { roc_mcs_dev_fini; roc_mcs_dev_get; roc_mcs_hw_info_get; + roc_mcs_rsrc_alloc; + roc_mcs_rsrc_free; + roc_mcs_sa_policy_read; + roc_mcs_sa_policy_write; roc_nix_bpf_alloc; roc_nix_bpf_config; roc_nix_bpf_connect; -- 2.25.1