From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id F006A42CC8; Thu, 15 Jun 2023 18:55:02 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 709F442BAC; Thu, 15 Jun 2023 18:54:55 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id D633340A8B for ; Thu, 15 Jun 2023 18:54:51 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686848092; x=1718384092; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Yxbzunms18syWZVeq+gNJI010fvkf3C527McxhLRsY=; b=WubdynMJb6wa1i9J413daZ4EpvW7fulRHpUgOvo2jQdCqWI6p34LbNmX GUBcn3nAjqIP9cImjm4XqdLmf6O0vuTiXAL6K5/EryBQGpoUYWG4+DYZK 0CKUWac7G9+Aq0M3iFFFUtWen4O0SiLwjeOpHNsE1KdPeZH9rxpSe16jX YI4QmHfbgAxHLdMi+HrIj6Z4ZZ8a/P8DMB/IbkWc0ynYV0aA6KSWg7Aq9 dK8sbidrwWYV6yhYJGhxEXqtr77uQeFjUD8Hqd0+K3k43l3BMa908r1a4 2HxY8u4vDEuc27pnFAHonMsHz5dAbwCLOJQk4I5U3Ven2z75ta5uU/QdY A==; X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="356469817" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="356469817" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 09:54:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="712518719" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="712518719" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by orsmga002.jf.intel.com with ESMTP; 15 Jun 2023 09:54:28 -0700 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: trix@redhat.com, hemant.agrawal@nxp.com, david.marchand@redhat.com, hernan.vargas@intel.com, Nicolas Chautru Subject: [PATCH v2 3/5] bbdev: add new capability for FEC 5G UL processing Date: Thu, 15 Jun 2023 16:48:59 +0000 Message-Id: <20230615164901.40845-4-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615164901.40845-1-nicolas.chautru@intel.com> References: <20230615164901.40845-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Extending existing LDPC UL operation for new capability. Option to compress HARQ memory to 4 bits per LLR. Signed-off-by: Nicolas Chautru --- doc/guides/prog_guide/bbdev.rst | 6 ++++++ lib/bbdev/rte_bbdev_op.h | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/doc/guides/prog_guide/bbdev.rst b/doc/guides/prog_guide/bbdev.rst index 95b33562fe..c43e478eda 100644 --- a/doc/guides/prog_guide/bbdev.rst +++ b/doc/guides/prog_guide/bbdev.rst @@ -903,6 +903,12 @@ given below. |RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK | | Set if a device supports loopback access to HARQ internal memory | +--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS | +| Set if a device includes LLR filler bits in HARQ circular buffer | ++--------------------------------------------------------------------+ +|RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION | +|Set if a device supports input/output 4 bits HARQ compression | ++--------------------------------------------------------------------+ The structure passed for each LDPC decode operation is given below, with the operation flags forming a bitmask in the ``op_flags`` field. diff --git a/lib/bbdev/rte_bbdev_op.h b/lib/bbdev/rte_bbdev_op.h index 682e265327..a4a2ae1440 100644 --- a/lib/bbdev/rte_bbdev_op.h +++ b/lib/bbdev/rte_bbdev_op.h @@ -203,7 +203,9 @@ enum rte_bbdev_op_ldpcdec_flag_bitmasks { * for HARQ memory. If not set, it is assumed the filler bits are not * in HARQ memory and handled directly by the LDPC decoder. */ - RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 19) + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS = (1ULL << 19), + /** Set if a device supports input/output HARQ 4bits compression. */ + RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION = (1ULL << 20) }; /** Flags for LDPC encoder operation and capability structure */ -- 2.34.1