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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2023 14:11:47.5505 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad04ad46-b800-4a51-4b21-08db71984902 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8830 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org AES-GCM provides both authenticated encryption and the ability to check the integrity and authentication of additional authenticated data (AAD) that is sent in the clear. The crypto operations are performed with crypto WQE. If the input buffers(AAD, mbuf, digest) are not contiguous and there is no enough headroom or tailroom for AAD or digest, as the requirement from FW, an UMR WQE is needed to generate contiguous address space for crypto WQE. The UMR WQE and crypto WQE are handled in two different QPs. The QP for UMR operation contains two types of WQE, UMR and SEND_EN WQE. The WQEs are built dynamically according to the crypto operation buffer address. Crypto operation with non-contiguous buffers will have its own UMR WQE, while the operation with contiguous buffers doesn't need the UMR WQE. Once the all the operations WQE in the enqueue burst built finishes, if any UMR WQEs are built, additional SEND_EN WQE will be as the final WQE of the burst in the UMR QP. The purpose of that SEND_EN WQE is to trigger the crypto QP processing with the UMR ready input memory address space buffers. The QP for crypto operations contains only the crypto WQE and the QP WQEs are built as fixed in QP setup. The QP processing is triggered by doorbell ring or the SEND_EN WQE from UMR QP. v2: - split XTS and GCM code to different file. - add headroom and tailroom optimize. v3: - fix AES-GCM 128b key creation. v4: - add missing feature cap in mlx5.ini Suanming Mou (9): common/mlx5: export memory region lookup by address crypto/mlx5: split AES-XTS crypto/mlx5: add AES-GCM query and initialization crypto/mlx5: add AES-GCM encryption key crypto/mlx5: add AES-GCM session configure common/mlx5: add WQE-based QP synchronous basics crypto/mlx5: add queue pair setup for GCM crypto/mlx5: add enqueue and dequeue operations crypto/mlx5: enable AES-GCM capability doc/guides/cryptodevs/features/mlx5.ini | 2 + doc/guides/cryptodevs/mlx5.rst | 48 +- doc/guides/rel_notes/release_23_07.rst | 1 + drivers/common/mlx5/mlx5_common_mr.c | 2 +- drivers/common/mlx5/mlx5_common_mr.h | 5 + drivers/common/mlx5/mlx5_devx_cmds.c | 21 + drivers/common/mlx5/mlx5_devx_cmds.h | 16 + drivers/common/mlx5/mlx5_prm.h | 65 +- drivers/common/mlx5/version.map | 3 + drivers/crypto/mlx5/meson.build | 2 + drivers/crypto/mlx5/mlx5_crypto.c | 673 ++-------------- drivers/crypto/mlx5/mlx5_crypto.h | 101 ++- drivers/crypto/mlx5/mlx5_crypto_dek.c | 102 ++- drivers/crypto/mlx5/mlx5_crypto_gcm.c | 997 ++++++++++++++++++++++++ drivers/crypto/mlx5/mlx5_crypto_xts.c | 645 +++++++++++++++ 15 files changed, 2018 insertions(+), 665 deletions(-) create mode 100644 drivers/crypto/mlx5/mlx5_crypto_gcm.c create mode 100644 drivers/crypto/mlx5/mlx5_crypto_xts.c -- 2.25.1