From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1238A42D09; Tue, 20 Jun 2023 16:12:03 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id ED3C042D3E; Tue, 20 Jun 2023 16:12:00 +0200 (CEST) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2049.outbound.protection.outlook.com [40.107.244.49]) by mails.dpdk.org (Postfix) with ESMTP id A01D742D29 for ; Tue, 20 Jun 2023 16:11:59 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nRyCpM+tBiUmsIdx2o2WnVXGv31tEL/ZdWz9+fDyZF8B9WT10EQoijUcj5kf/QlLLcf/zO8FdOHAlTkHXvXyhmBUJHIlbUhY/kUdfgG1Sh/wWUsW/l3vDcFqn+w12aPKuf3hgc1WC9dF3HzGdEtq/AUq3bHfeIuLrD86VE2sZmJfT5mMk7pip+xxGVYl+aqtNKmP8MFhObCThqtQjqDur0Nu4hht96Lz4njvTOMbpGAsEw3ify0fpjW5sGeuHJVIczlNBaIjyjHo/wjYfkncGJlKtYHWQ0Wd5JQXDWJaX5vKXX62r7Oe1PXs4V8S9MwPOdrCm3aM9TFZypmEP7jwfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=SMv8qoVE1679s4LC+HSXI2V4Ik0WbGcp84m6plvqtUo=; b=W8Rfz3XyVlFxFxNGD2wPdqvjg2BxLaMEwYV16XlUGnEG8E1bHfVf4GhXEpk15ry0zVhKuBvctjzKFK1nyU0e1+sEtKCnVvrv1/YM10spoUjul0VG5YC671KxVEh2TAtRhfIPQP4STZ0htWm5VnM/xOXGBSVOhohinpIxS4t4k8wZMkPkIzl/IWZ2c8ZnkRYboyVSJZ/oKzt2tV1FKHZou9gj7tvoM2GmoFtuQwMG+TAY2AAKiK7I+jNy5lp0fW0U4O3v+i6ZlnoPUvm+B127lCcvNg+MYik/SyY9UIwIjHbHJaxUkn33o9QhAnd/yH7TEry42pA/RyUORGJk/mzJ0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SMv8qoVE1679s4LC+HSXI2V4Ik0WbGcp84m6plvqtUo=; b=R36O97VapAfIWqIynDVd1HWr/vVcJD9/1YdL6RWM5A0HPEfF/69gxghvnOuSAJeb75RXCIxxbCFdnJcKOj4vw1xNx7T9w23HptY5yYbZX+SwkKqxOIU9TunAg7ea6Iu19CI1YYPajqYvC4a3IQ3i7+G/8U6wcixFiCQGlf+/a9JLnEzAC3+aFrgljJfa5ZDJbhS1icQPXsQs4nuLtIbjubxxkcTdYDhivdSt0uGXA5vWAwyzKsmf6OESUQrS/0e01TYBmucV+yM0swaib/Z2RUhavYWBF6vhg7eJwWXUtUHLFFxi2MXbWOKg/2uP0920CWD1vSIOREgNsS0degROkw== Received: from SJ0PR05CA0034.namprd05.prod.outlook.com (2603:10b6:a03:33f::9) by MW4PR12MB6827.namprd12.prod.outlook.com (2603:10b6:303:20b::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.35; Tue, 20 Jun 2023 14:11:57 +0000 Received: from MWH0EPF000989E8.namprd02.prod.outlook.com (2603:10b6:a03:33f:cafe::6a) by SJ0PR05CA0034.outlook.office365.com (2603:10b6:a03:33f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.21 via Frontend Transport; Tue, 20 Jun 2023 14:11:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by MWH0EPF000989E8.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.17 via Frontend Transport; Tue, 20 Jun 2023 14:11:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 20 Jun 2023 07:11:40 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 20 Jun 2023 07:11:37 -0700 From: Suanming Mou To: , Matan Azrad , Viacheslav Ovsiienko , Ori Kam CC: , Subject: [PATCH v4 3/9] crypto/mlx5: add AES-GCM query and initialization Date: Tue, 20 Jun 2023 17:11:09 +0300 Message-ID: <20230620141115.841226-4-suanmingm@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230620141115.841226-1-suanmingm@nvidia.com> References: <20230418092325.2578712-1-suanmingm@nvidia.com> <20230620141115.841226-1-suanmingm@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E8:EE_|MW4PR12MB6827:EE_ X-MS-Office365-Filtering-Correlation-Id: 5a3b8d55-c433-4fc1-7c47-08db71984ece X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lWGYSNp80ryWhqLpt1IEGnveYBA4EVUoe/sLNdvoFwA1WNZu4syvtENv7PTCWmMM/KFjTkUhkDGGKZqayM35S5CAJZS50rG1aKVHMOA/Ij9KYC0EVov6CZQD6TdXiEjqDWuUs6LWvGH8wDoF8kYfMxpPJ0N3XuKupkxwFqaw2w69vUjhgIa5LM1PbZBmfIRadBNXtJUTQIoHcLhq7Il4D82TsZGWnpCq4cyvcB2zuERhUKskibJYQ9pNsZ4fDqM4PfIkjbZ4DK5R8gdWdNq1sWREzTgfcPgyEHWVw8VDMZIrNbb54V8VIejXISJ1BS4hEaJyL1G2IT6bftAsLS9kteA+Kj71buKMV3V3japBrsJob6NmFZOqHVdKPbyw5m7/m/2/whTEDax3biTCF8Qmr/ONxtoY5CYHxiqoFfLsaaCdNRSmqEGckRERszfFpavRSsb1guel+xOzdZAXknr585ADmk6TD6lanEWkYJPCIM927mhVPwXbGkGoq4O0fL++Mti9yB7sY+EDUCDoIi8kYk3d6HZy/tfko8AiLyOAj3WCFlVERXAOOCwUkonZF/xO9oe21qTRCQywjf14OLHdKfWSiVwN7yJdRk6PBUGRAPO2bn7bmlZKEuBfRlUG9YoqJmRK400hpTTGVrnooClxVFUeTSJLifxWRFFfoKZZ4hY7QaIjCKApBj6AJiaJBJDtQ2gwhvz72gIxP7bQVBXwTaqmofRn59AcY2AF4x+H2NSGiVyAYav/9xfDXzmWra7z X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(396003)(136003)(39860400002)(376002)(346002)(451199021)(46966006)(40470700004)(36840700001)(478600001)(7636003)(70206006)(70586007)(36756003)(41300700001)(6636002)(8676002)(47076005)(356005)(2616005)(40480700001)(55016003)(4326008)(426003)(83380400001)(336012)(82310400005)(86362001)(2906002)(7696005)(5660300002)(6666004)(110136005)(54906003)(8936002)(316002)(26005)(1076003)(6286002)(40460700003)(186003)(16526019)(82740400003)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jun 2023 14:11:57.3242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a3b8d55-c433-4fc1-7c47-08db71984ece X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6827 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org AES-GCM provides both authenticated encryption and the ability to check the integrity and authentication of additional authenticated data (AAD) that is sent in the clear. This commit adds the AES-GCM attributes query and initialization function. Signed-off-by: Suanming Mou Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_devx_cmds.c | 15 +++++++++++ drivers/common/mlx5/mlx5_devx_cmds.h | 13 ++++++++++ drivers/common/mlx5/mlx5_prm.h | 19 +++++++++++--- drivers/crypto/mlx5/meson.build | 1 + drivers/crypto/mlx5/mlx5_crypto.c | 4 ++- drivers/crypto/mlx5/mlx5_crypto.h | 3 +++ drivers/crypto/mlx5/mlx5_crypto_gcm.c | 36 +++++++++++++++++++++++++++ 7 files changed, 87 insertions(+), 4 deletions(-) create mode 100644 drivers/crypto/mlx5/mlx5_crypto_gcm.c diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 1e418a0353..4332081165 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1117,6 +1117,21 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->crypto_wrapped_import_method = !!(MLX5_GET(crypto_caps, hcattr, wrapped_import_method) & 1 << 2); + attr->crypto_mmo.crypto_mmo_qp = MLX5_GET(crypto_caps, hcattr, crypto_mmo_qp); + attr->crypto_mmo.gcm_256_encrypt = + MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_encrypt); + attr->crypto_mmo.gcm_128_encrypt = + MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_encrypt); + attr->crypto_mmo.gcm_256_decrypt = + MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_256_decrypt); + attr->crypto_mmo.gcm_128_decrypt = + MLX5_GET(crypto_caps, hcattr, crypto_aes_gcm_128_decrypt); + attr->crypto_mmo.gcm_auth_tag_128 = + MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_128); + attr->crypto_mmo.gcm_auth_tag_96 = + MLX5_GET(crypto_caps, hcattr, gcm_auth_tag_96); + attr->crypto_mmo.log_crypto_mmo_max_size = + MLX5_GET(crypto_caps, hcattr, log_crypto_mmo_max_size); } if (hca_cap_2_sup) { hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index dc3359268d..cb3f3a211b 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -125,6 +125,18 @@ struct mlx5_hca_flex_attr { uint8_t header_length_mask_width; }; +__extension__ +struct mlx5_hca_crypto_mmo_attr { + uint32_t crypto_mmo_qp:1; + uint32_t gcm_256_encrypt:1; + uint32_t gcm_128_encrypt:1; + uint32_t gcm_256_decrypt:1; + uint32_t gcm_128_decrypt:1; + uint32_t gcm_auth_tag_128:1; + uint32_t gcm_auth_tag_96:1; + uint32_t log_crypto_mmo_max_size:6; +}; + /* ISO C restricts enumerator values to range of 'int' */ __extension__ enum { @@ -250,6 +262,7 @@ struct mlx5_hca_attr { struct mlx5_hca_vdpa_attr vdpa; struct mlx5_hca_flow_attr flow; struct mlx5_hca_flex_attr flex; + struct mlx5_hca_crypto_mmo_attr crypto_mmo; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 3d5b6b9ba5..e41b5b3528 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -4582,7 +4582,9 @@ struct mlx5_ifc_crypto_caps_bits { u8 synchronize_dek[0x1]; u8 int_kek_manual[0x1]; u8 int_kek_auto[0x1]; - u8 reserved_at_6[0x12]; + u8 reserved_at_6[0xd]; + u8 sw_wrapped_dek_key_purpose[0x1]; + u8 reserved_at_14[0x4]; u8 wrapped_import_method[0x8]; u8 reserved_at_20[0x3]; u8 log_dek_max_alloc[0x5]; @@ -4599,8 +4601,19 @@ struct mlx5_ifc_crypto_caps_bits { u8 log_dek_granularity[0x5]; u8 reserved_at_68[0x3]; u8 log_max_num_int_kek[0x5]; - u8 reserved_at_70[0x10]; - u8 reserved_at_80[0x780]; + u8 sw_wrapped_dek_new[0x10]; + u8 reserved_at_80[0x80]; + u8 crypto_mmo_qp[0x1]; + u8 crypto_aes_gcm_256_encrypt[0x1]; + u8 crypto_aes_gcm_128_encrypt[0x1]; + u8 crypto_aes_gcm_256_decrypt[0x1]; + u8 crypto_aes_gcm_128_decrypt[0x1]; + u8 gcm_auth_tag_128[0x1]; + u8 gcm_auth_tag_96[0x1]; + u8 reserved_at_107[0x3]; + u8 log_crypto_mmo_max_size[0x6]; + u8 reserved_at_110[0x10]; + u8 reserved_at_120[0x6e0]; }; struct mlx5_ifc_crypto_commissioning_register_bits { diff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build index 045e8ce81d..17ffce89f0 100644 --- a/drivers/crypto/mlx5/meson.build +++ b/drivers/crypto/mlx5/meson.build @@ -16,6 +16,7 @@ endif sources = files( 'mlx5_crypto.c', 'mlx5_crypto_xts.c', + 'mlx5_crypto_gcm.c', 'mlx5_crypto_dek.c', ) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 2e6bcc6ddc..ff632cd69a 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -335,7 +335,9 @@ mlx5_crypto_dev_probe(struct mlx5_common_device *cdev, rte_errno = ENOTSUP; return -rte_errno; } - if (!cdev->config.hca_attr.crypto || !cdev->config.hca_attr.aes_xts) { + if (!cdev->config.hca_attr.crypto || + (!cdev->config.hca_attr.aes_xts && + !cdev->config.hca_attr.crypto_mmo.crypto_mmo_qp)) { DRV_LOG(ERR, "Not enough capabilities to support crypto " "operations, maybe old FW/OFED version?"); rte_errno = ENOTSUP; diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 05d8fe97fe..76f368ee91 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -117,4 +117,7 @@ mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv); int mlx5_crypto_xts_init(struct mlx5_crypto_priv *priv); +int +mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv); + #endif /* MLX5_CRYPTO_H_ */ diff --git a/drivers/crypto/mlx5/mlx5_crypto_gcm.c b/drivers/crypto/mlx5/mlx5_crypto_gcm.c new file mode 100644 index 0000000000..bd78c6d66b --- /dev/null +++ b/drivers/crypto/mlx5/mlx5_crypto_gcm.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2023 NVIDIA Corporation & Affiliates + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mlx5_crypto_utils.h" +#include "mlx5_crypto.h" + +static struct rte_cryptodev_capabilities mlx5_crypto_gcm_caps[] = { + { + .op = RTE_CRYPTO_OP_TYPE_UNDEFINED, + }, + { + .op = RTE_CRYPTO_OP_TYPE_UNDEFINED, + } +}; + +int +mlx5_crypto_gcm_init(struct mlx5_crypto_priv *priv) +{ + priv->caps = mlx5_crypto_gcm_caps; + return 0; +} + -- 2.25.1