From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id AB78742D82; Wed, 28 Jun 2023 18:31:00 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B78D642D12; Wed, 28 Jun 2023 18:30:48 +0200 (CEST) Received: from mail-pl1-f179.google.com (mail-pl1-f179.google.com [209.85.214.179]) by mails.dpdk.org (Postfix) with ESMTP id 29CCF42D0E for ; Wed, 28 Jun 2023 18:30:46 +0200 (CEST) Received: by mail-pl1-f179.google.com with SMTP id d9443c01a7336-1b80512a7f2so670975ad.3 for ; Wed, 28 Jun 2023 09:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1687969845; x=1690561845; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:from:to:cc:subject:date:message-id:reply-to; bh=BgfOxicCKeDZ4wEzdr3M0loLoQjsYqKBFyyS4NRFz4Y=; b=D3cO8fWoGcvoZKmwoYLTXVohBNbWKirhYFcseS8Gh46k0q7f8tUbHUoWTlbnXXYaev 7mGvBjFOpWelVvfflMeVqWsNfWTgQIYqmQCBlE0dTWtqICenBZ+TBD1KxPN0mTnKHyM6 2Ig0hmsKB8hLpQ2dEjLqes2r1oOr/3DdL5Vkg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687969845; x=1690561845; h=mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=BgfOxicCKeDZ4wEzdr3M0loLoQjsYqKBFyyS4NRFz4Y=; b=MceLV4OMqAXlWEIyq1IZv8Ql51MvLuwKhHVFgGMPmyhnO5Os+UAdtPWk5AfstPKV6l vGVcaLgTKuWcMe1QMnpW+DeFFGyttoqga+/41vneEcR1Te0fvs641AOGxebyiJVCFotW KF0komsSPgZMf8t1zRqcAAGsAUBqcS2KpayDMI10fserHGbcW3M8ak/+JA23xiSZVwRx 4zm0WvSEOqjSfQ68Q4zVbrrLw9CtQjYRwaBjvE8WxmpwCewrK5TDmEpduF4IAjG6PWGI RSqrYSpUQSJIe9nwq+KcV8Ex4uKCZsZnK+EActQb8K9gKJp2eiIxFrnsSmEEh0Kp6b3S W0oQ== X-Gm-Message-State: AC+VfDwLfHMU+fcXd1kWXwcJdXJjoqElbTRMp7Bh84o6F4uASsKFCS7P vt2UFuylvJfVBe3DrX/wb1e0cbXflpcY9hPPe0GmunCOIqale7KHPV16PbE5+Hc7uMEuQ5VRJQo bE/sJshbkofW778tcPRGXKrb1ieCPcntqAED5trz9OibGIrMsX1LLkjYTzAN71EDw+TDFubc= X-Google-Smtp-Source: ACHHUZ6uBHxmvcTqvM31xcat4PMR7FhhZjq3+BdxJO0Xq/6r/gdFOk4pqIxRiDY772GkVtx/+MbEQw== X-Received: by 2002:a17:902:ecce:b0:1b5:561a:5ca9 with SMTP id a14-20020a170902ecce00b001b5561a5ca9mr12355571plh.50.1687969841496; Wed, 28 Jun 2023 09:30:41 -0700 (PDT) Received: from localhost.localdomain ([192.19.252.250]) by smtp.gmail.com with ESMTPSA id h12-20020a170902f7cc00b001b8229942a0sm3092403plw.34.2023.06.28.09.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Jun 2023 09:30:39 -0700 (PDT) From: Ajit Khaparde To: dev@dpdk.org Cc: ferruh.yigit@intel.com, thomas@monjalon.net, Randy Schacher , Kishore Padmanabha Subject: [PATCH v4 02/11] net/bnxt: update bnxt hsi structure Date: Wed, 28 Jun 2023 09:29:18 -0700 Message-Id: <20230628162927.92858-3-ajit.khaparde@broadcom.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230628162927.92858-1-ajit.khaparde@broadcom.com> References: <1826961.atdPhlSkOF@thomas> <20230628162927.92858-1-ajit.khaparde@broadcom.com> MIME-Version: 1.0 Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="00000000000005431605ff331b65" X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org --00000000000005431605ff331b65 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Randy Schacher Sync hsi structure to latest revision. New version is 1.10.2.138 Signed-off-by: Randy Schacher Reviewed-by: Kishore Padmanabha Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/hsi_struct_def_dpdk.h | 5723 +++++++++++++++++++++--- 1 file changed, 5128 insertions(+), 595 deletions(-) diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h index 380dec4d3e..9afdd056ce 100644 --- a/drivers/net/bnxt/hsi_struct_def_dpdk.h +++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * Copyright (c) 2014-2022 Broadcom Inc. + * Copyright (c) 2014-2023 Broadcom Inc. * All rights reserved. * * DO NOT MODIFY!!! This file is automatically generated. @@ -442,6 +442,8 @@ struct cmd_nums { #define HWRM_PORT_DSC_DUMP UINT32_C(0xd9) #define HWRM_PORT_EP_TX_QCFG UINT32_C(0xda) #define HWRM_PORT_EP_TX_CFG UINT32_C(0xdb) + #define HWRM_PORT_CFG UINT32_C(0xdc) + #define HWRM_PORT_QCFG UINT32_C(0xdd) #define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0) #define HWRM_REG_POWER_QUERY UINT32_C(0xe1) #define HWRM_CORE_FREQUENCY_QUERY UINT32_C(0xe2) @@ -480,9 +482,7 @@ struct cmd_nums { #define HWRM_CFA_FLOW_FREE UINT32_C(0x104) /* Experimental */ #define HWRM_CFA_FLOW_FLUSH UINT32_C(0x105) - /* Experimental */ #define HWRM_CFA_FLOW_STATS UINT32_C(0x106) - /* Experimental */ #define HWRM_CFA_FLOW_INFO UINT32_C(0x107) /* Experimental */ #define HWRM_CFA_DECAP_FILTER_ALLOC UINT32_C(0x108) @@ -678,6 +678,17 @@ struct cmd_nums { #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT UINT32_C(0x1a7) /* The is the new API to query backing store capabilities. */ #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 UINT32_C(0x1a8) + /* To query doorbell pacing NQ id list configuration. */ + #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY UINT32_C(0x1a9) + /* + * To notify the firmware that recovery cycle has been + * completed by host function drivers. + */ + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED UINT32_C(0x1aa) + /* Configures SyncE configurations. */ + #define HWRM_FUNC_SYNCE_CFG UINT32_C(0x1ab) + /* Queries SyncE configurations. */ + #define HWRM_FUNC_SYNCE_QCFG UINT32_C(0x1ac) /* Experimental */ #define HWRM_SELFTEST_QLIST UINT32_C(0x200) /* Experimental */ @@ -747,6 +758,8 @@ struct cmd_nums { * to run. */ #define HWRM_MFG_SELFTEST_EXEC UINT32_C(0x217) + /* Queries the generic stats */ + #define HWRM_STAT_GENERIC_QSTATS UINT32_C(0x218) /* Experimental */ #define HWRM_TF UINT32_C(0x2bc) /* Experimental */ @@ -774,6 +787,10 @@ struct cmd_nums { /* Experimental */ #define HWRM_TF_SESSION_RESC_INFO UINT32_C(0x2d0) /* Experimental */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET UINT32_C(0x2d1) + /* Experimental */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET UINT32_C(0x2d2) + /* Experimental */ #define HWRM_TF_TBL_TYPE_GET UINT32_C(0x2da) /* Experimental */ #define HWRM_TF_TBL_TYPE_SET UINT32_C(0x2db) @@ -819,6 +836,54 @@ struct cmd_nums { #define HWRM_TF_IF_TBL_SET UINT32_C(0x2fe) /* Experimental */ #define HWRM_TF_IF_TBL_GET UINT32_C(0x2ff) + /* TruFlow command to check firmware table scope capabilities. */ + #define HWRM_TFC_TBL_SCOPE_QCAPS UINT32_C(0x380) + /* TruFlow command to allocate a table scope ID and create the pools. */ + #define HWRM_TFC_TBL_SCOPE_ID_ALLOC UINT32_C(0x381) + /* TruFlow command to configure the table scope memory. */ + #define HWRM_TFC_TBL_SCOPE_CONFIG UINT32_C(0x382) + /* TruFlow command to deconfigure a table scope memory. */ + #define HWRM_TFC_TBL_SCOPE_DECONFIG UINT32_C(0x383) + /* TruFlow command to add a FID to a table scope. */ + #define HWRM_TFC_TBL_SCOPE_FID_ADD UINT32_C(0x384) + /* TruFlow command to remove a FID from a table scope. */ + #define HWRM_TFC_TBL_SCOPE_FID_REM UINT32_C(0x385) + /* TruFlow command to allocate a table scope pool. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC UINT32_C(0x386) + /* TruFlow command to free a table scope pool. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE UINT32_C(0x387) + /* Experimental */ + #define HWRM_TFC_SESSION_ID_ALLOC UINT32_C(0x388) + /* Experimental */ + #define HWRM_TFC_SESSION_FID_ADD UINT32_C(0x389) + /* Experimental */ + #define HWRM_TFC_SESSION_FID_REM UINT32_C(0x38a) + /* Experimental */ + #define HWRM_TFC_IDENT_ALLOC UINT32_C(0x38b) + /* Experimental */ + #define HWRM_TFC_IDENT_FREE UINT32_C(0x38c) + /* TruFlow command to allocate an index table entry */ + #define HWRM_TFC_IDX_TBL_ALLOC UINT32_C(0x38d) + /* TruFlow command to allocate and set an index table entry */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET UINT32_C(0x38e) + /* TruFlow command to set an index table entry */ + #define HWRM_TFC_IDX_TBL_SET UINT32_C(0x38f) + /* TruFlow command to get an index table entry */ + #define HWRM_TFC_IDX_TBL_GET UINT32_C(0x390) + /* TruFlow command to free an index table entry */ + #define HWRM_TFC_IDX_TBL_FREE UINT32_C(0x391) + /* TruFlow command to allocate resources for a global id. */ + #define HWRM_TFC_GLOBAL_ID_ALLOC UINT32_C(0x392) + /* TruFlow command to set TCAM entry. */ + #define HWRM_TFC_TCAM_SET UINT32_C(0x393) + /* TruFlow command to get TCAM entry. */ + #define HWRM_TFC_TCAM_GET UINT32_C(0x394) + /* TruFlow command to allocate a TCAM entry. */ + #define HWRM_TFC_TCAM_ALLOC UINT32_C(0x395) + /* TruFlow command allocate and set TCAM entry. */ + #define HWRM_TFC_TCAM_ALLOC_SET UINT32_C(0x396) + /* TruFlow command to free a TCAM entry. */ + #define HWRM_TFC_TCAM_FREE UINT32_C(0x397) /* Experimental */ #define HWRM_SV UINT32_C(0x400) /* Experimental */ @@ -1089,8 +1154,8 @@ struct hwrm_err_output { #define HWRM_VERSION_MINOR 10 #define HWRM_VERSION_UPDATE 2 /* non-zero means beta version */ -#define HWRM_VERSION_RSVD 83 -#define HWRM_VERSION_STR "1.10.2.83" +#define HWRM_VERSION_RSVD 138 +#define HWRM_VERSION_STR "1.10.2.138" /**************** * hwrm_ver_get * @@ -1345,6 +1410,7 @@ struct hwrm_ver_get_output { * If set to 1, firmware is capable to support flow aging. * If set to 0, firmware is not capable to support flow aging. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \ UINT32_C(0x200) @@ -1353,6 +1419,7 @@ struct hwrm_ver_get_output { * Meter drop counters and EEM counters. * If set to 0, firmware is not capable to support advanced flow counters. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \ UINT32_C(0x400) @@ -1362,6 +1429,7 @@ struct hwrm_ver_get_output { * If set to 0, firmware is not capable to support the use of the * CFA EEM feature. * By default, this flag should be 0 for older version of core firmware. + * (deprecated) */ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \ UINT32_C(0x800) @@ -1996,7 +2064,7 @@ struct cfa_bds_event_collect_cmd_data_msg { uint64_t host_address; } __rte_packed; -/* ce_bds_add_data_msg (size:512b/64B) */ +/* ce_bds_add_data_msg (size:576b/72B) */ struct ce_bds_add_data_msg { uint32_t version_algorithm_kid_opcode; /* @@ -2050,26 +2118,14 @@ struct ce_bds_add_data_msg { (UINT32_C(0x1) << 28) #define CE_BDS_ADD_DATA_MSG__LAST \ CE_BDS_ADD_DATA_MSG__TLS1_3 - uint8_t cmd_type_ctx_kind; - /* - * Command Type in the TLS header. HW will provide registers that - * converts the 3b encoded command type to 8b of actual command - * type in the TLS Header. This field is initialized/updated by - * this "KTLS crypto add" mid-path command. - */ - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_MASK UINT32_C(0x7) - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_SFT 0 - /* Application */ - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP UINT32_C(0x0) - #define CE_BDS_ADD_DATA_MSG_CMD_TYPE_LAST \ - CE_BDS_ADD_DATA_MSG_CMD_TYPE_APP + uint8_t ctx_kind; /* This field selects the context kind for the request. */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0xf8) - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 3 + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x1f) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_SFT 0 /* Crypto key transmit context */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX (UINT32_C(0x11) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_TX UINT32_C(0x11) /* Crypto key receive context */ - #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX (UINT32_C(0x12) << 3) + #define CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX UINT32_C(0x12) #define CE_BDS_ADD_DATA_MSG_CTX_KIND_LAST \ CE_BDS_ADD_DATA_MSG_CTX_KIND_CK_RX uint8_t unused0[3]; @@ -2083,8 +2139,8 @@ struct ce_bds_add_data_msg { * is zero padded to 12B and then xor'ed with the 4B of salt to generate * the 12B of IV. This value is initialized by this mid-path command. */ - uint32_t salt; - uint32_t unused1; + uint8_t salt[4]; + uint8_t unused1[4]; /* * This field keeps track of the TCP sequence number that is expected as * the first byte in the next TCP packet. This field is calculated by HW @@ -2111,16 +2167,21 @@ struct ce_bds_add_data_msg { * the field after that for every record processed as it parses the TCP * packet. */ - uint32_t record_seq_num[2]; + uint64_t record_seq_num; /* * Key used for encrypting or decrypting TLS records. The Key is * exchanged during the hand-shake protocol by the client-server and * provided to HW through this mid-path BD. */ - uint32_t session_key[8]; + uint8_t session_key[32]; + /* + * Additional IV that is exchanged as part of sessions setup between + * the two end points. This field is used for TLS1.3 only. + */ + uint8_t addl_iv[8]; } __rte_packed; -/* ce_bds_delete_data_msg (size:64b/8B) */ +/* ce_bds_delete_data_msg (size:32b/4B) */ struct ce_bds_delete_data_msg { uint32_t kid_opcode_ctx_kind; /* @@ -2160,7 +2221,6 @@ struct ce_bds_delete_data_msg { #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX (UINT32_C(0x15) << 24) #define CE_BDS_DELETE_DATA_MSG_CTX_KIND_LAST \ CE_BDS_DELETE_DATA_MSG_CTX_KIND_QUIC_RX - uint32_t unused0; } __rte_packed; /* ce_bds_resync_resp_ack_msg (size:128b/16B) */ @@ -2213,7 +2273,7 @@ struct ce_bds_resync_resp_ack_msg { * it has found since sending the resync request, update the context and * resume decrypting records. */ - uint32_t resync_record_seq_num[2]; + uint64_t resync_record_seq_num; } __rte_packed; /* ce_bds_resync_resp_nack_msg (size:64b/8B) */ @@ -2288,6 +2348,19 @@ struct crypto_presync_bd_cmd { */ #define CRYPTO_PRESYNC_BD_CMD_FLAGS_UPDATE_IN_ORDER_VAR \ UINT32_C(0x1) + /* + * When packet with an authentication TAG is lost in the network, + * During retransmission Device driver will post the entire record for + * the hardware to recalculate the TAG. Hardware is set to retransmit + * only portions of the record, it does so by looking at the Header + * TCP Sequence Number and Start TCP Sequence Number. However, there + * is a case where the header packet gets dropped in the stack for ex + * BPF packet filter and it is impossible for the Hardware to + * determine if this is a case of full replay for only the TAG + * generation. + */ + #define CRYPTO_PRESYNC_BD_CMD_FLAGS_FULL_REPLAY_RETRAN \ + UINT32_C(0x2) uint8_t unused0; uint16_t unused1; /* @@ -2331,7 +2404,7 @@ struct crypto_presync_bd_cmd { * the first TLS header. When subsequent TLS Headers are detected, the * value is extracted from packet. */ - uint32_t explicit_nonce[2]; + uint8_t explicit_nonce[8]; /* * This is sequence number for the TLS record in a particular session. In * TLS1.2, record sequence number is part of the Associated Data (AD) in @@ -2343,7 +2416,110 @@ struct crypto_presync_bd_cmd { * delivering more retransmission instruction will also update this * field. */ - uint32_t record_seq_num[2]; + uint64_t record_seq_num; +} __rte_packed; + +/* ce_bds_quic_add_data_msg (size:832b/104B) */ +struct ce_bds_quic_add_data_msg { + uint32_t ver_algo_kid_opcode; + /* + * This value selects the operation for the mid-path command for the + * crypto blocks. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_MASK UINT32_C(0xf) + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_SFT 0 + /* + * This is the add command. Using this opcode, Host Driver can add + * information required for QUIC processing. The information is + * updated in the CFCK context. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD UINT32_C(0x1) + #define CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_OPCODE_ADD + /* + * This field is the Crypto Context ID. The KID is used to store + * information used by the associated QUIC offloaded connection. + */ + #define CE_BDS_QUIC_ADD_DATA_MSG_KID_MASK \ + UINT32_C(0xfffff0) + #define CE_BDS_QUIC_ADD_DATA_MSG_KID_SFT 4 + /* Algorithm used for encryption and decryption. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_MASK \ + UINT32_C(0xf000000) + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_SFT 24 + /* AES_GCM_128 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_128 \ + (UINT32_C(0x1) << 24) + /* AES_GCM_256 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_AES_GCM_256 \ + (UINT32_C(0x2) << 24) + /* Chacha20 Algorithm. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 \ + (UINT32_C(0x3) << 24) + #define CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_ALGORITHM_CHACHA20 + /* Version number of QUIC connection. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_MASK \ + UINT32_C(0xf0000000) + #define CE_BDS_QUIC_ADD_DATA_MSG_VERSION_SFT 28 + /* TLS1.2 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_2 \ + (UINT32_C(0x0) << 28) + /* TLS1.3 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__TLS1_3 \ + (UINT32_C(0x1) << 28) + /* DTLS1.2 Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2 \ + (UINT32_C(0x2) << 28) + /* DTLS1.2 for RoCE Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__DTLS1_2_ROCE \ + (UINT32_C(0x3) << 28) + /* QUIC Version */ + #define CE_BDS_QUIC_ADD_DATA_MSG__QUIC \ + (UINT32_C(0x4) << 28) + #define CE_BDS_QUIC_ADD_DATA_MSG__LAST \ + CE_BDS_QUIC_ADD_DATA_MSG__QUIC + uint32_t ctx_kind_dcid_width_key_phase; + /* Key phase. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_KEY_PHASE UINT32_C(0x1) + /* Destination connection ID width. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_MASK UINT32_C(0x3e) + #define CE_BDS_QUIC_ADD_DATA_MSG_DCID_WIDTH_SFT 1 + /* This field selects the context kind for the request. */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_MASK UINT32_C(0x7c0) + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_SFT 6 + /* QUIC key transmit context */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_TX \ + (UINT32_C(0x14) << 6) + /* QUIC key receive context */ + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX \ + (UINT32_C(0x15) << 6) + #define CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_LAST \ + CE_BDS_QUIC_ADD_DATA_MSG_CTX_KIND_QUIC_RX + uint32_t unused_0[2]; + /* + * Least-significant 64 bits (of 96) of additional IV that is + * exchanged as part of sessions setup between the two end + * points for QUIC operations. + */ + uint64_t quic_iv_lo; + /* + * Most-significant 32 bits (of 96) of additional IV that is + * exchanged as part of sessions setup between the two end + * points for QUIC operations. + */ + uint32_t quic_iv_hi; + uint32_t unused_1; + /* + * Key used for encrypting or decrypting records. The Key is exchanged + * as part of sessions setup between the two end points through this + * mid-path BD. + */ + uint32_t session_key[8]; + /* Header protection key. */ + uint32_t hp_key[8]; + /* Packet number associated with the QUIC connection. */ + uint64_t pkt_number; } __rte_packed; /* bd_base (size:64b/8B) */ @@ -3665,7 +3841,7 @@ struct cfa_dma128b_data_msg { /* ce_cmpls_cmp_data_msg (size:128b/16B) */ struct ce_cmpls_cmp_data_msg { - uint16_t status_subtype_type; + uint16_t client_subtype_type; /* * This field indicates the exact type of the completion. By * convention, the LSB identifies the length of the record in 16B @@ -3678,82 +3854,82 @@ struct ce_cmpls_cmp_data_msg { #define CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT UINT32_C(0x1e) #define CE_CMPLS_CMP_DATA_MSG_TYPE_LAST \ CE_CMPLS_CMP_DATA_MSG_TYPE_MID_PATH_SHORT + #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_MASK UINT32_C(0xc0) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED0_SFT 6 /* * This value indicates the CE sub-type operation that is being * completed. */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0x3c0) - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 6 + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_MASK UINT32_C(0xf00) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SFT 8 /* Completion Response for a Solicited Command. */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_SOLICITED (UINT32_C(0x0) << 8) /* Error Completion (Unsolicited). */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_ERR (UINT32_C(0x1) << 8) /* Re-Sync Completion (Unsolicited) */ - #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 6) + #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC (UINT32_C(0x2) << 8) #define CE_CMPLS_CMP_DATA_MSG_SUBTYPE_LAST \ CE_CMPLS_CMP_DATA_MSG_SUBTYPE_RESYNC + /* + * This field represents the Mid-Path client that generated the + * completion. + */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_MASK UINT32_C(0xf000) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_SFT 12 + /* TX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_TCE \ + (UINT32_C(0x0) << 12) + /* RX crypto engine block. */ + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE \ + (UINT32_C(0x1) << 12) + #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_LAST \ + CE_CMPLS_CMP_DATA_MSG_MP_CLIENT_RCE + uint16_t status; /* This value indicates the status for the command. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0x3c00) - #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 10 + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MASK UINT32_C(0xf) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_SFT 0 /* Completed without error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK \ - (UINT32_C(0x0) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_OK UINT32_C(0x0) /* CFCK load error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR \ - (UINT32_C(0x1) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_LD_ERR UINT32_C(0x1) /* FID check error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR \ - (UINT32_C(0x2) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_FID_CHK_ERR UINT32_C(0x2) /* Context kind / MP version mismatch error. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR \ - (UINT32_C(0x3) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_CTX_VER_ERR UINT32_C(0x3) /* Unsupported Destination Connection ID Length. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR \ - (UINT32_C(0x4) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_DST_ID_ERR UINT32_C(0x4) /* * Invalid MP Command [anything other than ADD or DELETE * triggers this for QUIC]. */ - #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR \ - (UINT32_C(0x5) << 10) + #define CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR UINT32_C(0x5) #define CE_CMPLS_CMP_DATA_MSG_STATUS_LAST \ CE_CMPLS_CMP_DATA_MSG_STATUS_MP_CMD_ERR - uint8_t unused0; - uint8_t mp_clients; - #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xf) - #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 0 - /* - * This field represents the Mid-Path client that generated the - * completion. - */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_MASK UINT32_C(0xf0) - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_SFT 4 - /* TX crypto engine block. */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_TCE (UINT32_C(0x0) << 4) - /* RX crypto engine block. */ - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE (UINT32_C(0x1) << 4) - #define CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_LAST \ - CE_CMPLS_CMP_DATA_MSG_MP_CLIENTS_RCE + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_MASK UINT32_C(0xfff0) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED1_SFT 4 /* * This is a copy of the opaque field from the mid path BD of this * command. */ uint32_t opaque; - /* */ - uint32_t kid_v; + uint32_t v; /* * This value is written by the NIC such that it will be different * for each pass through the completion queue. The even passes will * write 1. The odd passes will write 0. */ - #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CE_CMPLS_CMP_DATA_MSG_V UINT32_C(0x1) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_MASK UINT32_C(0xfffffffe) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED2_SFT 1 + uint32_t kid; /* * This field is the Crypto Context ID. The KID is used to store * information used by the associated kTLS offloaded connection. */ - #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0x1ffffe) - #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 1 - uint32_t unused2; + #define CE_CMPLS_CMP_DATA_MSG_KID_MASK UINT32_C(0xfffff) + #define CE_CMPLS_CMP_DATA_MSG_KID_SFT 0 + #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_MASK UINT32_C(0xfff00000) + #define CE_CMPLS_CMP_DATA_MSG_UNUSED3_SFT 20 } __rte_packed; /* cmpl_base (size:128b/16B) */ @@ -3783,16 +3959,11 @@ struct cmpl_base { * Completion of coalesced TX packet. Length = 16B */ #define CMPL_BASE_TYPE_TX_L2_COAL UINT32_C(0x2) - /* - * TX L2 PTP completion: - * Completion of PTP TX packet. Length = 32B - */ - #define CMPL_BASE_TYPE_TX_L2_PTP UINT32_C(0x3) /* * TX L2 Packet Timestamp completion: * Completion of an L2 Packet Timestamp Packet. Length = 16B */ - #define CMPL_BASE_TYPE_TX_L2_PTP_TS UINT32_C(0x4) + #define CMPL_BASE_TYPE_TX_L2_PKT_TS UINT32_C(0x4) /* * RX L2 TPA Start V2 Completion: * Completion of and L2 RX packet. Length = 32B @@ -4173,47 +4344,79 @@ struct tx_cmpl_coal { #define TX_CMPL_COAL_SQ_CONS_IDX_SFT 0 } __rte_packed; -/* tx_cmpl_ptp (size:128b/16B) */ -struct tx_cmpl_ptp { - uint16_t flags_type; +/* tx_cmpl_packet_timestamp (size:128b/16B) */ +struct tx_cmpl_packet_timestamp { + uint16_t ts_sub_ns_flags_type; /* - * This field indicates the exact type of the completion. - * By convention, the LSB identifies the length of the - * record in 16B units. Even values indicate 16B - * records. Odd values indicate 32B - * records. + * This field indicates the exact type of the completion. By + * convention, the LSB identifies the length of the record in 16B + * units. Even values indicate 16B records. Odd values indicate + * 32B records. */ - #define TX_CMPL_PTP_TYPE_MASK UINT32_C(0x3f) - #define TX_CMPL_PTP_TYPE_SFT 0 + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_MASK UINT32_C(0x3f) + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_SFT 0 /* - * TX L2 PTP completion: - * Completion of TX packet. Length = 32B + * TX L2 Packet Timestamp completion: + * Completion of an L2 Packet Timestamp Packet. Length = 16B */ - #define TX_CMPL_PTP_TYPE_TX_L2_PTP UINT32_C(0x2) - #define TX_CMPL_PTP_TYPE_LAST TX_CMPL_PTP_TYPE_TX_L2_PTP - #define TX_CMPL_PTP_FLAGS_MASK UINT32_C(0xffc0) - #define TX_CMPL_PTP_FLAGS_SFT 6 + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS UINT32_C(0x4) + #define TX_CMPL_PACKET_TIMESTAMP_TYPE_LAST \ + TX_CMPL_PACKET_TIMESTAMP_TYPE_TX_L2_PKT_TS + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_MASK UINT32_C(0xfc0) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_SFT 6 /* - * When this bit is '1', it indicates a packet that has an - * error of some type. Type of error is indicated in - * error_flags. + * When this bit is '1', it indicates a packet that has an error + * of some type. Type of error is indicated in error_flags. */ - #define TX_CMPL_PTP_FLAGS_ERROR UINT32_C(0x40) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_ERROR UINT32_C(0x40) /* - * When this bit is '1', it indicates that the packet completed - * was transmitted using the push acceleration data provided - * by the driver. When this bit is '0', it indicates that the - * packet had not push acceleration data written or was executed - * as a normal packet even though push data was provided. + * This field indicates the TX packet timestamp type that is + * represented by a TX Packet Timestamp Completion. Note that + * this field is invalid if the timestamp_invalid_error flag + * is set. */ - #define TX_CMPL_PTP_FLAGS_PUSH UINT32_C(0x80) - /* unused1 is 16 b */ - uint16_t unused_0; + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE UINT32_C(0x80) + /* The packet timestamp came from PM. */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PM \ + (UINT32_C(0x0) << 7) + /* The packet timestamp came from PA. */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA \ + (UINT32_C(0x1) << 7) + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_LAST \ + TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_TYPE_TS_PA + /* + * This flag indicates that the timestamp should have come from PM, + * but came instead from PA because all PM timestamp resources were + * in use. This can occur in the following circumstances: + * 1. The BD specified ts_2cmpl_auto and the packet was a PTP packet + * but PA could not request a PM timestamp + * 2. The BD specified ts_2cmpl_pm, but PA could not request a PM + * timestamp + */ + #define TX_CMPL_PACKET_TIMESTAMP_FLAGS_TS_FALLBACK UINT32_C(0x100) + /* + * For 2-step PTP timestamps, bits[3:0] of this field represent the + * sub-nanosecond portion of the packet timestamp, returned from PM + * for 2-step PTP timestamps. For PA timestamps, this field also + * represents the sub-nanosecond portion of the packet timestamp; + * however, due to synchronization uncertainties, the accuracy of + * PA timestamps is limited to approximately +/- 4 ns. Therefore + * this field is of dubious value for PA timestamps. + */ + #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_MASK UINT32_C(0xf000) + #define TX_CMPL_PACKET_TIMESTAMP_TS_SUB_NS_SFT 12 + /* + * This is bits [47:32] of the nanoseconds portion of the packet + * timestamp, returned from PM for 2-step PTP timestamps or from + * PA for PA timestamps. This field is in units of 2^32 ns. + */ + uint16_t ts_ns_mid; /* * This is a copy of the opaque field from the first TX BD of this - * transmitted packet. Note that, if the packet was described by a short - * CSO or short CSO inline BD, then the 16-bit opaque field from the - * short CSO BD will appear in the bottom 16 bits of this field. + * transmitted packet. Note that, if the packet was described by a + * short CSO or short CSO inline BD, then the 16-bit opaque field + * from the short CSO BD will appear in the bottom 16 bits of this + * field. */ uint32_t opaque; uint16_t errors_v; @@ -4222,95 +4425,103 @@ struct tx_cmpl_ptp { * for each pass through the completion queue. The even passes * will write 1. The odd passes will write 0. */ - #define TX_CMPL_PTP_V UINT32_C(0x1) - #define TX_CMPL_PTP_ERRORS_MASK UINT32_C(0xfffe) - #define TX_CMPL_PTP_ERRORS_SFT 1 + #define TX_CMPL_PACKET_TIMESTAMP_V \ + UINT32_C(0x1) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_MASK \ + UINT32_C(0xfffe) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_SFT 1 /* - * This error indicates that there was some sort of problem - * with the BDs for the packet. + * This field was previously used to indicate fatal errors, which + * now result in aborting and bringing down the ring. This field + * is deprecated. */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe) - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_SFT 1 - /* No error */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_NO_ERROR \ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_MASK \ + UINT32_C(0xe) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_SFT 1 + /* No error. */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_NO_ERROR \ (UINT32_C(0x0) << 1) - /* - * Bad Format: - * BDs were not formatted correctly. - */ - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT \ + /* Deprecated. */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT \ (UINT32_C(0x2) << 1) - #define TX_CMPL_PTP_ERRORS_BUFFER_ERROR_LAST \ - TX_CMPL_PTP_ERRORS_BUFFER_ERROR_BAD_FMT + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_LAST \ + TX_CMPL_PACKET_TIMESTAMP_ERRORS_BUFFER_ERROR_BAD_FMT /* - * When this bit is '1', it indicates that the length of - * the packet was zero. No packet was transmitted. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_ZERO_LENGTH_PKT UINT32_C(0x10) - /* - * When this bit is '1', it indicates that the packet - * was longer than the programmed limit in TDI. No - * packet was transmitted. - */ - #define TX_CMPL_PTP_ERRORS_EXCESSIVE_BD_LENGTH UINT32_C(0x20) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_ZERO_LENGTH_PKT \ + UINT32_C(0x10) /* - * When this bit is '1', it indicates that one or more of the - * BDs associated with this packet generated a PCI error. - * This probably means the address was not valid. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_DMA_ERROR UINT32_C(0x40) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_EXCESSIVE_BD_LENGTH \ + UINT32_C(0x20) /* - * When this bit is '1', it indicates that the packet was longer - * than indicated by the hint. No packet was transmitted. + * When this bit is '1', it indicates that one or more of the BDs + * associated with this packet generated a PCI error when accessing + * header/payload data from host memory. It most likely indicates + * that the address was not valid. Note that this bit has no meaning + * for the timestamp completion and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_HINT_TOO_SHORT UINT32_C(0x80) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_DMA_ERROR \ + UINT32_C(0x40) /* - * When this bit is '1', it indicates that the packet was - * dropped due to Poison TLP error on one or more of the - * TLPs in the PXP completion. + * This error is fatal and results in aborting and bringing down the + * ring, thus is deprecated. */ - #define TX_CMPL_PTP_ERRORS_POISON_TLP_ERROR UINT32_C(0x100) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_HINT_TOO_SHORT \ + UINT32_C(0x80) /* - * When this bit is '1', it indicates that the packet was dropped due - * to a transient internal error in TDC. The packet or LSO can be - * retried and may transmit successfully on a subsequent attempt. + * When this bit is '1', it indicates that the packet was dropped + * due to Poison TLP error on one or more of the TLPs in one or more + * of the associated PXP completion(s) when accessing header/payload + * data from host memory. Note that this bit has no meaning for the + * timestamp completion, and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_INTERNAL_ERROR UINT32_C(0x200) + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_POISON_TLP_ERROR \ + UINT32_C(0x100) /* - * When this bit is '1', it was not possible to collect a a timestamp - * for a PTP completion, in which case the timestamp_hi and - * timestamp_lo fields are invalid. When this bit is '0' for a PTP - * completion, the timestamp_hi and timestamp_lo fields are valid. - * RJRN will copy the value of this bit into the field of the same - * name in all TX completions, regardless of whether such - * completions are PTP completions or other TX completions. + * When this bit is '1', it indicates that the packet was dropped + * due to a transient internal error in TDC. The packet or LSO can + * be retried and may transmit successfully on a subsequent attempt. + * Note that this bit has no meaning for the timestamp completion + * and will always be '0'. */ - #define TX_CMPL_PTP_ERRORS_TIMESTAMP_INVALID_ERROR UINT32_C(0x400) - /* unused2 is 16 b */ - uint16_t unused_1; + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_INTERNAL_ERROR \ + UINT32_C(0x200) /* - * This is timestamp value (lower 32bits) read from PM for the PTP - * timestamp enabled packet. - */ - uint32_t timestamp_lo; -} __rte_packed; - -/* tx_cmpl_ptp_hi (size:128b/16B) */ -struct tx_cmpl_ptp_hi { + * When this bit is '1', it was not possible to collect a timestamp + * for a timestamp completion, in which case the ts_ns and ts_sub_ns + * fields are invalid. When this bit is '0' in a timestamp + * completion record, the ts_sub_ns, ts_ns_lo, and ts_ns_mid fields + * are valid. Note that this bit has meaning only for the timestamp + * completion. For types other than the timestamp completion, this + * bit will always be '0'. + */ + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TIMESTAMP_INVALID_ERROR \ + UINT32_C(0x400) /* - * This is timestamp value (lower 32bits) read from PM for the PTP - * timestamp enabled packet. + * When this bit is '1', it indicates that a Timed Transmit + * SO-TXTIME packet violated the max_ttx_overtime constraint i.e., + * the time the packet was processed for transmission in TWE was + * later than the time given by (TimedTx_BD.tx_time + + * max_ttx_overtime) and as result, the packet was dropped. + * Note that max_ttx_overtime is a global configuration in TWE. + * Note that this bit has no meaning in a timestamp completion, + * and will always be '0'. */ - uint16_t timestamp_hi[3]; - uint16_t reserved16; - uint64_t v2; + #define TX_CMPL_PACKET_TIMESTAMP_ERRORS_TTX_OVERTIME_ERROR \ + UINT32_C(0x800) + /* unused2 is 16 b */ + uint16_t unused_2; /* - * This value is written by the NIC such that it will be different for - * each pass through the completion queue. - * The even passes will write 1. - * The odd passes will write 0. + * This is bits [31:0] of the nanoseconds portion of the packet + * timestamp, returned from PM for 2-step PTP timestamp or from + * PA for PA timestamps. This field is in units of ns. */ - #define TX_CMPL_PTP_HI_V2 UINT32_C(0x1) + uint32_t ts_ns_lo; } __rte_packed; /* rx_pkt_cmpl (size:128b/16B) */ @@ -9314,9 +9525,31 @@ struct hwrm_async_event_cmpl { */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD \ UINT32_C(0x46) + /* + * An event from firmware indicating that the RSS capabilities have + * changed. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE \ + UINT32_C(0x47) + /* + * An event from firmware indicating that list of nq ids used for + * doorbell pacing DBQ event notification has been updated. The driver + * needs to take appropriate action and retrieve the new list when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \ + UINT32_C(0x48) + /* + * An event from firmware indicating that hardware ran into an error + * while trying to read the host based doorbell copy region. The driver + * needs to take the appropriate action and maintain the corresponding + * doorbell copy region. + */ + #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \ + UINT32_C(0x49) /* Maximum Registrable event id. */ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \ - UINT32_C(0x47) + UINT32_C(0x4a) /* * A trace log message. This contains firmware trace logs string * embedded in the asynchronous message. This is an experimental @@ -11828,6 +12061,195 @@ struct hwrm_async_event_cmpl_doorbell_pacing_threshold { uint32_t event_data1; } __rte_packed; +/* hwrm_async_event_cmpl_rss_change (size:128b/16B) */ +struct hwrm_async_event_cmpl_rss_change { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_SFT 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the driver + * that the RSS capabilities have changed. The driver will need + * to query hwrm_vnic_qcaps. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE \ + UINT32_C(0x47) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_EVENT_ID_RSS_CHANGE + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_V UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_MASK UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_RSS_CHANGE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_doorbell_pacing_nq_update (size:128b/16B) */ +struct hwrm_async_event_cmpl_doorbell_pacing_nq_update { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * An event from firmware indicating that list of nq ids used for + * doorbell pacing DBQ event notification has been updated. The driver + * needs to take appropriate action and retrieve the new list when this + * event is received from the firmware. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE \ + UINT32_C(0x48) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_EVENT_ID_DOORBELL_PACING_NQ_UPDATE + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_DOORBELL_PACING_NQ_UPDATE_OPAQUE_SFT 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; +} __rte_packed; + +/* hwrm_async_event_cmpl_hw_doorbell_recovery_read_error (size:128b/16B) */ +struct hwrm_async_event_cmpl_hw_doorbell_recovery_read_error { + uint16_t type; + /* + * This field indicates the exact type of the completion. + * By convention, the LSB identifies the length of the + * record in 16B units. Even values indicate 16B + * records. Odd values indicate 32B + * records. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_MASK \ + UINT32_C(0x3f) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_SFT \ + 0 + /* HWRM Asynchronous Event Information */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT \ + UINT32_C(0x2e) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_TYPE_HWRM_ASYNC_EVENT + /* Identifiers of events. */ + uint16_t event_id; + /* + * This async notification message is used to inform the driver + * that hardware ran into an error while trying to read the host + * based doorbell copy region. The driver will take the appropriate + * action to maintain the corresponding functions doorbell copy + * region in the correct format. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR \ + UINT32_C(0x49) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_LAST \ + HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR + /* Event specific data. */ + uint32_t event_data2; + uint8_t opaque_v; + /* + * This value is written by the NIC such that it will be different + * for each pass through the completion queue. The even passes + * will write 1. The odd passes will write 0. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_V \ + UINT32_C(0x1) + /* opaque is 7 b */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_MASK \ + UINT32_C(0xfe) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_OPAQUE_SFT \ + 1 + /* 8-lsb timestamp (100-msec resolution) */ + uint8_t timestamp_lo; + /* 16-lsb timestamp (100-msec resolution) */ + uint16_t timestamp_hi; + /* Event specific data */ + uint32_t event_data1; + /* + * Indicates that there is an error while reading the doorbell copy + * regions. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_MASK \ + UINT32_C(0xf) + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SFT \ + 0 + /* + * If set to 1, indicates that there is an error while reading the + * SQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SQ_ERR \ + UINT32_C(0x1) + /* + * If set to 1, indicates that there is an error while reading the + * RQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_RQ_ERR \ + UINT32_C(0x2) + /* + * If set to 1, indicates that there is an error while reading the + * SRQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_SRQ_ERR \ + UINT32_C(0x4) + /* + * If set to 1, indicates that there is an error while reading the + * CQ doorbell copy region for this function. + */ + #define HWRM_ASYNC_EVENT_CMPL_HW_DOORBELL_RECOVERY_READ_ERROR_EVENT_DATA1_READ_ERROR_FLAGS_CQ_ERR \ + UINT32_C(0x8) +} __rte_packed; + /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */ struct hwrm_async_event_cmpl_fw_trace_msg { uint16_t type; @@ -12385,6 +12807,14 @@ struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { UINT32_C(0x4) #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST \ HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD + /* + * The epoch value to be sent from firmware to the driver to track + * a doorbell recovery cycle. + */ + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK \ + UINT32_C(0xffffff00) + #define HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT \ + 8 } __rte_packed; /* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ @@ -12516,8 +12946,8 @@ struct metadata_base_msg { #define METADATA_BASE_MSG_MD_TYPE_NONE UINT32_C(0x0) /* * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * the state of the receive context, the meta-data will carry + * different information. */ #define METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC UINT32_C(0x1) /* @@ -12525,12 +12955,21 @@ struct metadata_base_msg { * record that it is requesting a resync on in the meta data. */ #define METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC UINT32_C(0x2) + /* This setting is used for QUIC packets. */ + #define METADATA_BASE_MSG_MD_TYPE_QUIC UINT32_C(0x3) + /* + * This setting is used for crypto packets with an unsupported + * protocol. + */ + #define METADATA_BASE_MSG_MD_TYPE_ILLEGAL UINT32_C(0x1f) #define METADATA_BASE_MSG_MD_TYPE_LAST \ - METADATA_BASE_MSG_MD_TYPE_TLS_RESYNC + METADATA_BASE_MSG_MD_TYPE_ILLEGAL /* - * This field indicates where the next metadata block starts. It is - * counted in 16B units. A value of zero indicates that there is no - * metadata. + * This field indicates where the next metadata block starts, relative + * to the current metadata block. It is the offset to the next metadata + * header, counted in 16B units. A value of zero indicates that there is + * no additional metadata, and that the current metadata block is the + * last one. */ #define METADATA_BASE_MSG_LINK_MASK UINT32_C(0x1e0) #define METADATA_BASE_MSG_LINK_SFT 5 @@ -12544,11 +12983,12 @@ struct tls_metadata_base_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_BASE_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_BASE_MSG_MD_TYPE_SFT \ + 0 /* - * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * This setting is used when packets are coming in-order. Depending + * on the state of the receive context, the meta-data will carry + * different information. */ #define TLS_METADATA_BASE_MSG_MD_TYPE_TLS_INSYNC \ UINT32_C(0x1) @@ -12567,11 +13007,13 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_BASE_MSG_LINK_SFT 5 + #define TLS_METADATA_BASE_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_BASE_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_BASE_MSG_FLAGS_SFT 9 + #define TLS_METADATA_BASE_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12584,7 +13026,8 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_BASE_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12610,12 +13053,13 @@ struct tls_metadata_base_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_BASE_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) /* * This enumeration states that there is at least one tag in the @@ -12638,13 +13082,61 @@ struct tls_metadata_base_msg { */ #define TLS_METADATA_BASE_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_BASE_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_BASE_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_BASE_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_BASE_MSG_KID_LO_SFT 25 + #define TLS_METADATA_BASE_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -12661,11 +13153,12 @@ struct tls_metadata_insync_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_INSYNC_MSG_MD_TYPE_SFT \ + 0 /* * This setting is used when packets are coming in-order. Depending on - * the state of the receive context, the meta-data will carry different - * information. + * the state of the receive context, the meta-data will carry + * different information. */ #define TLS_METADATA_INSYNC_MSG_MD_TYPE_TLS_INSYNC \ UINT32_C(0x1) @@ -12678,11 +13171,13 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_INSYNC_MSG_LINK_SFT 5 + #define TLS_METADATA_INSYNC_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_INSYNC_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT 9 + #define TLS_METADATA_INSYNC_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12695,7 +13190,8 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_INSYNC_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12721,12 +13217,13 @@ struct tls_metadata_insync_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_INSYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) /* * This enumeration states that there is at least one tag in the @@ -12749,13 +13246,61 @@ struct tls_metadata_insync_msg { */ #define TLS_METADATA_INSYNC_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_INSYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_INSYNC_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT 25 + #define TLS_METADATA_INSYNC_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -12764,14 +13309,14 @@ struct tls_metadata_insync_msg { #define TLS_METADATA_INSYNC_MSG_KID_HI_MASK UINT32_C(0x1fff) #define TLS_METADATA_INSYNC_MSG_KID_HI_SFT 0 /* - * This field is only valid when md_type is set to tls_insync. This field - * indicates the offset within the current TCP packet where the TLS header - * starts. If there are multiple TLS headers in the packet, this provides - * the offset of the last TLS header. + * This field is only valid when md_type is set to tls_insync. This + * field indicates the offset within the current TCP packet where the + * TLS header starts. If there are multiple TLS headers in the packet, + * this provides the offset of the last TLS header. * - * The field is calculated by subtracting TCP sequence number of the first - * byte of the TCP payload of the packet from the TCP sequence number of - * the last TLS header in the packet. + * The field is calculated by subtracting TCP sequence number of the + * first byte of the TCP payload of the packet from the TCP sequence + * number of the last TLS header in the packet. */ uint16_t tls_header_offset; /* @@ -12787,7 +13332,7 @@ struct tls_metadata_insync_msg { * not decrypt every packet and authenticate the record. Partial GHASH is * only sent out with packet having the TAG field. */ - uint64_t partial_ghash; + uint8_t partial_ghash[8]; } __rte_packed; /* tls_metadata_resync_msg (size:256b/32B) */ @@ -12796,7 +13341,8 @@ struct tls_metadata_resync_msg { /* This field classifies the data present in the meta-data. */ #define TLS_METADATA_RESYNC_MSG_MD_TYPE_MASK \ UINT32_C(0x1f) - #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT 0 + #define TLS_METADATA_RESYNC_MSG_MD_TYPE_SFT \ + 0 /* * With this setting HW passes the TCP sequence number of the TLS * record that it is requesting a resync on in the meta data. @@ -12812,11 +13358,13 @@ struct tls_metadata_resync_msg { */ #define TLS_METADATA_RESYNC_MSG_LINK_MASK \ UINT32_C(0x1e0) - #define TLS_METADATA_RESYNC_MSG_LINK_SFT 5 + #define TLS_METADATA_RESYNC_MSG_LINK_SFT \ + 5 /* These are flags present in the metadata. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_MASK \ UINT32_C(0x1fffe00) - #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT 9 + #define TLS_METADATA_RESYNC_MSG_FLAGS_SFT \ + 9 /* * A value of 1 implies that the packet was decrypted by HW. Otherwise * the packet is passed on as it came in on the wire. @@ -12829,7 +13377,8 @@ struct tls_metadata_resync_msg { */ #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_MASK \ UINT32_C(0xc00) - #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT 10 + #define TLS_METADATA_RESYNC_MSG_FLAGS_GHASH_SFT \ + 10 /* * This enumeration states that the ghash is not valid in the * meta-data. @@ -12841,28 +13390,77 @@ struct tls_metadata_resync_msg { /* This field indicates the status of tag authentication. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_MASK \ UINT32_C(0x3000) - #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT 12 + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_SFT \ + 12 /* - * This enumeration is set when there is no tags present in the - * packet. + * This enumeration is set when HW was not able to authenticate a + * TAG. */ - #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE \ + #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED \ (UINT32_C(0x0) << 12) #define TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_LAST \ - TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NONE + TLS_METADATA_RESYNC_MSG_FLAGS_TAG_AUTH_STATUS_NOT_CHECKED /* * A value of 1 indicates that this packet contains a record that * starts in the packet and extends beyond the packet. */ #define TLS_METADATA_RESYNC_MSG_FLAGS_HEADER_FLDS_VALID \ UINT32_C(0x4000) + /* + * A value of 1 indicates that the packet experienced a context load + * error. In this case, the packet is sent to the host without the + * header or payload decrypted and the context is not updated. + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_CTX_LOAD_ERR \ + UINT32_C(0x8000) + /* This field indicates the packet operation state. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_MASK \ + UINT32_C(0x70000) + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_SFT \ + 16 + /* Packet is in order. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_IN_ORDER \ + (UINT32_C(0x0) << 16) + /* Packet is out of order, no header loss. */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_OUT_OF_ORDER \ + (UINT32_C(0x1) << 16) + /* Packet is header search (out of order with header loss). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_HEADER_SEARCH \ + (UINT32_C(0x2) << 16) + /* Packet is resync (resync record ongoing). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC \ + (UINT32_C(0x3) << 16) + /* + * Packet is resync wait (resync record completes, waiting for + * result). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT \ + (UINT32_C(0x4) << 16) + /* + * Packet is resync wait for partial tag (waiting for resync record + * tag). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_WAIT_PARTIAL \ + (UINT32_C(0x5) << 16) + /* Packet is resync success (got resync record success). */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS \ + (UINT32_C(0x6) << 16) + /* + * Packet is resync success wait (got midpath ACK, waiting for + * resync record success). + */ + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT \ + (UINT32_C(0x7) << 16) + #define TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_LAST \ + TLS_METADATA_RESYNC_MSG_FLAGS_PKT_OPERATION_STATE_RESYNC_SUCCESS_WAIT /* * This value indicates the lower 7-bit of the Crypto Key ID * associated with this operation. */ #define TLS_METADATA_RESYNC_MSG_KID_LO_MASK \ UINT32_C(0xfe000000) - #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT 25 + #define TLS_METADATA_RESYNC_MSG_KID_LO_SFT \ + 25 uint16_t kid_hi; /* * This value indicates the upper 13-bit of the Crypto Key ID @@ -13221,7 +13819,7 @@ struct hwrm_func_vf_free_output { ********************/ -/* hwrm_func_vf_cfg_input (size:448b/56B) */ +/* hwrm_func_vf_cfg_input (size:512b/64B) */ struct hwrm_func_vf_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -13384,7 +13982,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of TX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ @@ -13393,7 +13991,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ @@ -13402,7 +14000,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of CMPL rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ @@ -13411,7 +14009,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RSS ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ @@ -13420,7 +14018,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of ring groups) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ @@ -13429,7 +14027,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of stat ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ @@ -13438,7 +14036,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of VNICs) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ @@ -13447,7 +14045,7 @@ struct hwrm_func_vf_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of L2 ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_VF_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ @@ -13486,9 +14084,10 @@ struct hwrm_func_vf_cfg_input { /* The number of HW ring groups requested for the VF. */ uint16_t num_hw_ring_grps; /* Number of Tx Key Contexts requested. */ - uint16_t num_tx_key_ctxs; + uint32_t num_tx_key_ctxs; /* Number of Rx Key Contexts requested. */ - uint16_t num_rx_key_ctxs; + uint32_t num_rx_key_ctxs; + uint8_t unused[4]; } __rte_packed; /* hwrm_func_vf_cfg_output (size:128b/16B) */ @@ -13558,7 +14157,7 @@ struct hwrm_func_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcaps_output (size:768b/96B) */ +/* hwrm_func_qcaps_output (size:896b/112B) */ struct hwrm_func_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14176,6 +14775,74 @@ struct hwrm_func_qcaps_output { /* When this bit is '1', it indicates that HW and FW support QUIC. */ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_QUIC_SUPPORTED \ UINT32_C(0x2) + /* + * When this bit is '1', it indicates that KDNet mode is + * supported on the port for this function. This bit is + * never set for a VF. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_KDNET_SUPPORTED \ + UINT32_C(0x4) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting Enhanced Doorbell Pacing. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED \ + UINT32_C(0x8) + /* + * When this bit is '1', it indicates that FW is capable of + * supporting software based doorbell drop recovery. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED \ + UINT32_C(0x10) + /* + * When this bit is '1', it indicates the FW supports collection + * and query of the generic statistics. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_GENERIC_STATS_SUPPORTED \ + UINT32_C(0x20) + /* + * When this bit is '1', it indicates that the HW is capable of + * supporting UDP GSO on the function. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_UDP_GSO_SUPPORTED \ + UINT32_C(0x40) + /* + * When this bit is '1', it indicates that SyncE feature is + * supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_SYNCE_SUPPORTED \ + UINT32_C(0x80) + /* + * When this bit is '1', it indicates the FW is capable of + * supporting doorbell pacing version 0. As doorbell pacing + * notification from hardware for Thor2 is completely different + * from Thor1, this flag is used to differentiate the doorbell + * pacing notification between Thor1 and Thor2. Thor1 uses + * dbr_pacing_supported and dbr_pacing_ext_supported flags for + * doorbell pacing whereas Thor2 uses dbr_pacing_v0_supported flag. + * These flags will never be set at the same time for Thor2. + * Based on this flag, host drivers assume doorbell pacing is needed + * for Thor2. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED \ + UINT32_C(0x100) + /* + * When this bit is '1', it indicates that the HW supports + * two-completion TX packet timestamp feature, a second completion + * carrying packet TX timestamp in addition to the standard + * completion returned for packets. Host driver should not use + * HWRM port timestamp query (HWRM_PORT_TS_QUERY) command for + * TX timestamp read when two-completion timestamp feature is + * supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED \ + UINT32_C(0x200) + /* + * When this bit is '1', it indicates that the hardware based + * link aggregation group (L2 and RoCE) feature is supported. + */ + #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT2_HW_LAG_SUPPORTED \ + UINT32_C(0x400) uint16_t tunnel_disable_flag; /* * When this bit is '1', it indicates that the VXLAN parsing @@ -14225,7 +14892,16 @@ struct hwrm_func_qcaps_output { */ #define HWRM_FUNC_QCAPS_OUTPUT_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE \ UINT32_C(0x80) - uint8_t unused_1; + uint8_t unused_1[2]; + /* + * This value uniquely identifies the hardware NIC used by the + * function. The value returned will be the same for all functions. + * A value of 00-00-00-00-00-00-00-00 indicates no device serial number + * is currently configured. This is the same value that is returned by + * PCIe Capability Device Serial Number. + */ + uint8_t device_serial_number[8]; + uint8_t unused_2[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14283,7 +14959,7 @@ struct hwrm_func_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_qcfg_output (size:896b/112B) */ +/* hwrm_func_qcfg_output (size:1024b/128B) */ struct hwrm_func_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -14787,7 +15463,36 @@ struct hwrm_func_qcfg_output { */ #define HWRM_FUNC_QCFG_OUTPUT_MPC_CHNLS_PRIMATE_ENABLED \ UINT32_C(0x10) - uint8_t unused_2[3]; + /* + * Configured doorbell page size for this function. + * This field is valid for PF only. + */ + uint8_t db_page_size; + /* DB page size is 4KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0) + /* DB page size is 8KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1) + /* DB page size is 16KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2) + /* DB page size is 32KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3) + /* DB page size is 64KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4) + /* DB page size is 128KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5) + /* DB page size is 256KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6) + /* DB page size is 512KB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7) + /* DB page size is 1MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8) + /* DB page size is 2MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9) + /* DB page size is 4MB. */ + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) + #define HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_DB_PAGE_SIZE_4MB + uint8_t unused_2[2]; /* * Minimum guaranteed bandwidth for the network partition made up * of the caller physical function and all its child virtual @@ -14874,11 +15579,36 @@ struct hwrm_func_qcfg_output { * value is used if ring MTU is not specified. */ uint16_t host_mtu; + uint8_t unused_3[2]; + uint8_t unused_4[2]; + /* + * KDNet mode for the port for this function. If a VF, KDNet + * mode is always disabled. + */ + uint8_t port_kdnet_mode; + /* KDNet mode is not enabled on the port for this function. */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0) + /* KDNet mode is enabled on the port for this function. */ + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_LAST \ + HWRM_FUNC_QCFG_OUTPUT_PORT_KDNET_MODE_ENABLED + /* + * If KDNet mode is enabled, the PCI function number of the + * KDNet partition. + */ + uint8_t kdnet_pcie_function; + /* + * Function ID of the KDNET function on this port. If the + * KDNET partition does not exist and the FW supports this + * feature, 0xffff will be returned. + */ + uint16_t port_kdnet_fid; + uint8_t unused_5[2]; /* Number of Tx Key Contexts allocated. */ - uint16_t alloc_tx_key_ctxs; + uint32_t alloc_tx_key_ctxs; /* Number of Rx Key Contexts allocated. */ - uint16_t alloc_rx_key_ctxs; - uint8_t unused_3[5]; + uint32_t alloc_rx_key_ctxs; + uint8_t unused_6[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -14894,7 +15624,7 @@ struct hwrm_func_qcfg_output { *****************/ -/* hwrm_func_cfg_input (size:896b/112B) */ +/* hwrm_func_cfg_input (size:1024b/128B) */ struct hwrm_func_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -15002,7 +15732,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of TX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_TX_ASSETS_TEST \ @@ -15011,7 +15741,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RX rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RX_ASSETS_TEST \ @@ -15020,7 +15750,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of CMPL rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_CMPL_ASSETS_TEST \ @@ -15029,7 +15759,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of RSS ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RSSCOS_CTX_ASSETS_TEST \ @@ -15038,7 +15768,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of ring groups) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_RING_GRP_ASSETS_TEST \ @@ -15047,7 +15777,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of stat ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_STAT_CTX_ASSETS_TEST \ @@ -15056,7 +15786,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of VNICs) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_VNIC_ASSETS_TEST \ @@ -15065,7 +15795,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of L2 ctx) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_L2_CTX_ASSETS_TEST \ @@ -15091,7 +15821,7 @@ struct hwrm_func_cfg_input { * This bit requests that the firmware test to see if all the assets * requested in this command (i.e. number of NQ rings) are available. * The firmware will return an error if the requested assets are - * not available. The firwmare will NOT reserve the assets if they + * not available. The firmware will NOT reserve the assets if they * are available. */ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \ @@ -15158,6 +15888,15 @@ struct hwrm_func_cfg_input { */ #define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \ UINT32_C(0x40000000) + /* + * If this bit is set to 1, the driver is requesting FW to see if + * all the assets requested in this command (i.e. number of KTLS/ + * QUIC key contexts) are available. The firmware will return an + * error if the requested assets are not available. The firmware + * will NOT reserve the assets if they are available. + */ + #define HWRM_FUNC_CFG_INPUT_FLAGS_KEY_CTX_ASSETS_TEST \ + UINT32_C(0x80000000) uint32_t enables; /* * This bit must be '1' for the admin_mtu field to be @@ -15803,11 +16542,71 @@ struct hwrm_func_cfg_input { * ring that is assigned to a function has a valid mtu. */ uint16_t host_mtu; + uint8_t unused_0[4]; + uint32_t enables2; + /* + * This bit must be '1' for the kdnet_mode field to be + * configured. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_KDNET UINT32_C(0x1) + /* + * This bit must be '1' for the db_page_size field to be + * configured. Legacy controller core FW may silently ignore + * the db_page_size programming request through this command. + */ + #define HWRM_FUNC_CFG_INPUT_ENABLES2_DB_PAGE_SIZE UINT32_C(0x2) + /* + * KDNet mode for the port for this function. If NPAR is + * also configured on this port, it takes precedence. KDNet + * mode is ignored for a VF. + */ + uint8_t port_kdnet_mode; + /* KDNet mode is not enabled. */ + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_DISABLED UINT32_C(0x0) + /* KDNet mode enabled. */ + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED UINT32_C(0x1) + #define HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_LAST \ + HWRM_FUNC_CFG_INPUT_PORT_KDNET_MODE_ENABLED + /* + * This field can be used by the PF driver to configure the doorbell + * page size. L2 driver can use different pages to ring the doorbell + * for L2 push operation. The doorbell page size should be configured + * to match the native CPU page size for proper RoCE and L2 doorbell + * operations. This value supersedes the older method of configuring + * the doorbell page size by the RoCE driver using the command queue + * method. The default is 4K. + */ + uint8_t db_page_size; + /* DB page size is 4KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4KB UINT32_C(0x0) + /* DB page size is 8KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_8KB UINT32_C(0x1) + /* DB page size is 16KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_16KB UINT32_C(0x2) + /* DB page size is 32KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_32KB UINT32_C(0x3) + /* DB page size is 64KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_64KB UINT32_C(0x4) + /* DB page size is 128KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_128KB UINT32_C(0x5) + /* DB page size is 256KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_256KB UINT32_C(0x6) + /* DB page size is 512KB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_512KB UINT32_C(0x7) + /* DB page size is 1MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_1MB UINT32_C(0x8) + /* DB page size is 2MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_2MB UINT32_C(0x9) + /* DB page size is 4MB. */ + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB UINT32_C(0xa) + #define HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_LAST \ + HWRM_FUNC_CFG_INPUT_DB_PAGE_SIZE_4MB + uint8_t unused_1[2]; /* Number of Tx Key Contexts requested. */ - uint16_t num_tx_key_ctxs; + uint32_t num_tx_key_ctxs; /* Number of Rx Key Contexts requested. */ - uint16_t num_rx_key_ctxs; - uint8_t unused_0[4]; + uint32_t num_rx_key_ctxs; + uint8_t unused_2[4]; } __rte_packed; /* hwrm_func_cfg_output (size:128b/16B) */ @@ -15900,24 +16699,27 @@ struct hwrm_func_qstats_input { * A privileged PF can query for other function's statistics. */ uint16_t fid; - /* This flags indicates the type of statistics request. */ uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This bit should be set to 1 when request is for only RoCE + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) /* - * flags should be set to 2 when request is for the counter mask, + * This bit should be set to 1 when request is for the counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) + /* + * This bit should be set to 1 when request is for only L2 + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. + */ + #define HWRM_FUNC_QSTATS_INPUT_FLAGS_L2_ONLY UINT32_C(0x4) uint8_t unused_0[5]; } __rte_packed; @@ -15992,7 +16794,18 @@ struct hwrm_func_qstats_output { uint64_t rx_agg_events; /* Number of aborted aggregations on the function. */ uint64_t rx_agg_aborts; - uint8_t unused_0[7]; + /* + * This field is the sequence of the statistics of a function being + * cleared. Firmware starts the sequence from zero. It increments + * the sequence number every time the statistics of the function + * are cleared, which can be triggered by a clear statistics request + * or by freeing all statistics contexts of the function. If a user + * is interested in knowing if the statistics have been cleared + * since the last query, it can keep track of this sequence number + * between queries. + */ + uint8_t clear_seq; + uint8_t unused_0[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -16045,24 +16858,20 @@ struct hwrm_func_qstats_ext_input { * A privileged PF can query for other function's statistics. */ uint16_t fid; - /* This flags indicates the type of statistics request. */ uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* - * flags should be set to 1 when request is for only RoCE statistics. - * This will be honored only if the caller_fid is a privileged PF. - * In all other cases FID and caller_fid should be the same. + * This bit should be set to 1 when request is for only RoCE + * statistics. This will be honored only if the caller_fid is + * a privileged PF. In all other cases FID and caller_fid should + * be the same. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_ROCE_ONLY UINT32_C(0x1) /* - * flags should be set to 2 when request is for the counter mask + * This bit should be set to 1 when request is for the counter mask * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) - #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_LAST \ - HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + #define HWRM_FUNC_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x2) uint8_t unused_0[1]; uint32_t enables; /* @@ -16418,6 +17227,14 @@ struct hwrm_func_drv_rgtr_input { */ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_NPAR_1_2_SUPPORT \ UINT32_C(0x200) + /* + * When this bit is 1, the function's driver is indicating the + * support for asymmetric queue configuration, such that queue + * ids and service profiles on TX side are not the same as the + * corresponding queue configuration on the RX side + */ + #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ASYM_QUEUE_CFG_SUPPORT \ + UINT32_C(0x400) uint32_t enables; /* * This bit must be '1' for the os_type field to be @@ -16979,7 +17796,7 @@ struct hwrm_func_resource_qcaps_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_resource_qcaps_output (size:512b/64B) */ +/* hwrm_func_resource_qcaps_output (size:576b/72B) */ struct hwrm_func_resource_qcaps_output { /* The specific error status for the command. */ uint16_t error_code; @@ -17054,15 +17871,16 @@ struct hwrm_func_resource_qcaps_output { */ #define HWRM_FUNC_RESOURCE_QCAPS_OUTPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + uint8_t unused_0[2]; /* Minimum guaranteed number of Tx Key Contexts */ - uint16_t min_tx_key_ctxs; + uint32_t min_tx_key_ctxs; /* Maximum non-guaranteed number of Tx Key Contexts */ - uint16_t max_tx_key_ctxs; + uint32_t max_tx_key_ctxs; /* Minimum guaranteed number of Rx Key Contexts */ - uint16_t min_rx_key_ctxs; + uint32_t min_rx_key_ctxs; /* Maximum non-guaranteed number of Rx Key Contexts */ - uint16_t max_rx_key_ctxs; - uint8_t unused_0[5]; + uint32_t max_rx_key_ctxs; + uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17078,7 +17896,7 @@ struct hwrm_func_resource_qcaps_output { *****************************/ -/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */ +/* hwrm_func_vf_resource_cfg_input (size:576b/72B) */ struct hwrm_func_vf_resource_cfg_input { /* The HWRM command request type. */ uint16_t req_type; @@ -17152,18 +17970,18 @@ struct hwrm_func_vf_resource_cfg_input { */ #define HWRM_FUNC_VF_RESOURCE_CFG_INPUT_FLAGS_MIN_GUARANTEED \ UINT32_C(0x1) + uint8_t unused_0[2]; /* Minimum guaranteed number of Tx Key Contexts */ - uint16_t min_tx_key_ctxs; + uint32_t min_tx_key_ctxs; /* Maximum non-guaranteed number of Tx Key Contexts */ - uint16_t max_tx_key_ctxs; + uint32_t max_tx_key_ctxs; /* Minimum guaranteed number of Rx Key Contexts */ - uint16_t min_rx_key_ctxs; + uint32_t min_rx_key_ctxs; /* Maximum non-guaranteed number of Rx Key Contexts */ - uint16_t max_rx_key_ctxs; - uint8_t unused_0[2]; + uint32_t max_rx_key_ctxs; } __rte_packed; -/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ +/* hwrm_func_vf_resource_cfg_output (size:320b/40B) */ struct hwrm_func_vf_resource_cfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -17190,10 +18008,10 @@ struct hwrm_func_vf_resource_cfg_output { /* Reserved number of ring groups */ uint16_t reserved_hw_ring_grps; /* Actual number of Tx Key Contexts reserved */ - uint16_t reserved_tx_key_ctxs; + uint32_t reserved_tx_key_ctxs; /* Actual number of Rx Key Contexts reserved */ - uint16_t reserved_rx_key_ctxs; - uint8_t unused_0[3]; + uint32_t reserved_rx_key_ctxs; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -17479,8 +18297,13 @@ struct hwrm_func_backing_store_qcaps_output { * function. */ uint32_t rkc_max_entries; + /* + * Additional number of RoCE QP context entries required for this + * function to support fast QP destroy feature. + */ + uint16_t fast_qpmd_qp_num_entries; /* Reserved for future. */ - uint8_t rsvd1[7]; + uint8_t rsvd1[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -20638,31 +21461,53 @@ struct hwrm_func_ptp_pin_qcfg_output { /* Type of function for Pin #2. */ uint8_t pin2_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT /* Type of function for Pin #3. */ uint8_t pin3_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_QCFG_OUTPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT uint8_t unused_0; /* * This field is used in Output records to indicate that the output @@ -20813,17 +21658,28 @@ struct hwrm_func_ptp_pin_cfg_input { /* Configure function for TSIO pin#2. */ uint8_t pin2_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT /* Enable or disable functionality of Pin #3. */ uint8_t pin3_state; /* Disabled */ @@ -20835,17 +21691,28 @@ struct hwrm_func_ptp_pin_cfg_input { /* Configure function for TSIO pin#3. */ uint8_t pin3_usage; /* No function is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE UINT32_C(0x0) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_NONE \ + UINT32_C(0x0) /* PPS IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN UINT32_C(0x1) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_IN \ + UINT32_C(0x1) /* PPS OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT UINT32_C(0x2) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_PPS_OUT \ + UINT32_C(0x2) /* SYNC IN is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN UINT32_C(0x3) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_IN \ + UINT32_C(0x3) /* SYNC OUT is configured. */ - #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT UINT32_C(0x4) + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT \ + UINT32_C(0x4) + /* SYNCE primary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT \ + UINT32_C(0x5) + /* SYNCE secondary clock OUT is configured. */ + #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT \ + UINT32_C(0x6) #define HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_LAST \ - HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNC_OUT + HWRM_FUNC_PTP_PIN_CFG_INPUT_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT uint8_t unused_0[4]; } __rte_packed; @@ -21130,12 +21997,25 @@ struct hwrm_func_ptp_ts_query_output { uint16_t resp_len; /* Timestamp value of last PPS event latched. */ uint64_t pps_event_ts; - /* PTM local timestamp value. */ - uint64_t ptm_res_local_ts; - /* PTM Master timestamp value. */ - uint64_t ptm_pmstr_ts; - /* PTM Master propagation delay */ - uint32_t ptm_mstr_prop_dly; + /* + * PHC timestamp value when PTM responseD request is received + * at downstream port (t4'). This is a 48 bit timestamp in nanoseconds. + */ + uint64_t ptm_local_ts; + /* + * PTM System timestamp value corresponding to t4' at + * root complex (T4'). Together with ptm_local_ts, these + * two timestamps provide the cross-trigger timestamps. + * Driver can directly use these values for cross-trigger. + * This is a 48 bit timestamp in nanoseconds. + */ + uint64_t ptm_system_ts; + /* + * PTM Link delay. This is the time taken at root complex (RC) + * between receiving PTM request and sending PTM response to + * downstream port. This is a 32 bit value in nanoseconds. + */ + uint32_t ptm_link_delay; uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -21463,7 +22343,18 @@ struct hwrm_func_key_ctx_alloc_output { uint16_t resp_len; /* Actual number of Key Contexts allocated. */ uint16_t num_key_ctxs_allocated; - uint8_t unused_0[5]; + /* Control flags. */ + uint8_t flags; + /* + * When set, it indicates that all key contexts allocated by this + * command are contiguous. As a result, the driver has to read the + * start context ID from the first entry of the DMA data buffer + * and figures out the end context ID by “start context ID + + * num_key_ctxs_allocated - 1”. + */ + #define HWRM_FUNC_KEY_CTX_ALLOC_OUTPUT_FLAGS_KEY_CTXS_CONTIGUOUS \ + UINT32_C(0x1) + uint8_t unused_0[4]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -21574,6 +22465,9 @@ struct hwrm_func_backing_store_cfg_v2_input { * Instance of the backing store type. It is zero-based, * which means "0" indicates the first instance. For backing * stores with single instance only, leave this field to 0. + * 1. If the backing store type is MPC TQM ring, use the following + * instance value to MPC client mapping: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) */ uint16_t instance; /* Control flags. */ @@ -21586,6 +22480,31 @@ struct hwrm_func_backing_store_cfg_v2_input { */ #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_PREBOOT_MODE \ UINT32_C(0x1) + /* + * When set, the driver indicates that the backing store type + * to be configured in this command is the last one to do for + * the associated PF. That means all backing store type + * configurations are done for the corresponding PF after this + * command. As a result, the firmware has to do the necessary + * post configurations. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_CFG_ALL_DONE \ + UINT32_C(0x2) + /* + * When set, the driver indicates extending the size of the specific + * backing store type instead of configuring the corresponding PBLs. + * The size specified in the command will be the new size to be + * configured. The operation is only valid when the specific backing + * store has been configured before. Otherwise, the firmware will + * return an error. The driver needs to zero out the “entry_size”, + * “flags”, “page_dir”, and “page_size_pbl_level” fields, and the + * firmware will ignore these inputs. Further, the firmware expects + * the “num_entries” and any valid split entries to be no less than + * the initial value that has been configured. If not, it will + * return an error code. + */ + #define HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_FLAGS_BS_EXTEND \ + UINT32_C(0x4) /* Page directory. */ uint64_t page_dir; /* Number of entries */ @@ -21957,6 +22876,52 @@ struct hwrm_func_backing_store_qcfg_v2_output { uint8_t valid; } __rte_packed; +/* Common structure to cast QPC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is QPC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* qpc_split_entries (size:128b/16B) */ +struct qpc_split_entries { + /* Number of L2 QP backing store entries. */ + uint32_t qp_num_l2_entries; + /* Number of QP1 entries. */ + uint32_t qp_num_qp1_entries; + uint32_t rsvd[2]; +} __rte_packed; + +/* Common structure to cast SRQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is SRQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* srq_split_entries (size:128b/16B) */ +struct srq_split_entries { + /* Number of L2 SRQ backing store entries. */ + uint32_t srq_num_l2_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast CQ split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is CQ. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* cq_split_entries (size:128b/16B) */ +struct cq_split_entries { + /* Number of L2 CQ backing store entries. */ + uint32_t cq_num_l2_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast VNIC split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is VNIC. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* vnic_split_entries (size:128b/16B) */ +struct vnic_split_entries { + /* Number of VNIC backing store entries. */ + uint32_t vnic_num_vnic_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + +/* Common structure to cast MRAV split entries. This casting is required in the following HWRM command inputs/outputs if the backing store type is MRAV. 1. hwrm_func_backing_store_cfg_v2_input 2. hwrm_func_backing_store_qcfg_v2_output 3. hwrm_func_backing_store_qcaps_v2_output */ +/* mrav_split_entries (size:128b/16B) */ +struct mrav_split_entries { + /* Number of AV backing store entries. */ + uint32_t mrav_num_av_entries; + uint32_t rsvd; + uint32_t rsvd2[2]; +} __rte_packed; + /************************************ * hwrm_func_backing_store_qcaps_v2 * ************************************/ @@ -22150,6 +23115,9 @@ struct hwrm_func_backing_store_qcaps_v2_output { /* * Bit map of the valid instances associated with the * backing store type. + * 1. If the backing store type is MPC TQM ring, use the following + * bit to MPC client mapping: + * TCE (0), RCE (1), TE_CFA(2), RE_CFA (3), PRIMATE(4) */ uint32_t instance_bit_map; /* @@ -22506,7 +23474,7 @@ struct hwrm_func_dbr_pacing_qcfg_output { uint8_t unused_3[7]; /* * Specifies primary function’s NQ ID. - * A value of 0xFFFF indicates NQ ID is invalid. + * A value of 0xFFFF FFFF indicates NQ ID is invalid. */ uint32_t primary_nq_id; /* @@ -22585,13 +23553,13 @@ struct hwrm_func_dbr_pacing_broadcast_event_output { uint8_t valid; } __rte_packed; -/*********************** - * hwrm_func_vlan_qcfg * - ***********************/ +/************************************* + * hwrm_func_dbr_pacing_nqlist_query * + *************************************/ -/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ -struct hwrm_func_vlan_qcfg_input { +/* hwrm_func_dbr_pacing_nqlist_query_input (size:128b/16B) */ +struct hwrm_func_dbr_pacing_nqlist_query_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -22620,18 +23588,10 @@ struct hwrm_func_vlan_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* - * Function ID of the function that is being - * configured. - * If set to 0xFF... (All Fs), then the configuration is - * for the requesting function. - */ - uint16_t fid; - uint8_t unused_0[6]; } __rte_packed; -/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ -struct hwrm_func_vlan_qcfg_output { +/* hwrm_func_dbr_pacing_nqlist_query_output (size:384b/48B) */ +struct hwrm_func_dbr_pacing_nqlist_query_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -22640,49 +23600,414 @@ struct hwrm_func_vlan_qcfg_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint64_t unused_0; - /* S-TAG VLAN identifier configured for the function. */ - uint16_t stag_vid; - /* S-TAG PCP value configured for the function. */ - uint8_t stag_pcp; - uint8_t unused_1; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id0; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id1; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id2; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id3; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id4; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id5; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id6; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id7; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id8; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id9; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id10; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id11; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id12; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id13; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id14; + /* ID of an NQ ring allocated for DBR pacing notifications. */ + uint16_t nq_ring_id15; + /* Number of consecutive NQ ring IDs populated in the response. */ + uint32_t num_nqs; + uint8_t unused_0[3]; /* - * S-TAG TPID value configured for the function. This field is specified in - * network byte order. + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. */ - uint16_t stag_tpid; - /* C-TAG VLAN identifier configured for the function. */ - uint16_t ctag_vid; - /* C-TAG PCP value configured for the function. */ - uint8_t ctag_pcp; - uint8_t unused_2; + uint8_t valid; +} __rte_packed; + +/************************************ + * hwrm_func_dbr_recovery_completed * + ************************************/ + + +/* hwrm_func_dbr_recovery_completed_input (size:192b/24B) */ +struct hwrm_func_dbr_recovery_completed_input { + /* The HWRM command request type. */ + uint16_t req_type; /* - * C-TAG TPID value configured for the function. This field is specified in - * network byte order. + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. */ - uint16_t ctag_tpid; - /* Future use. */ - uint32_t rsvd2; - /* Future use. */ - uint32_t rsvd3; - uint8_t unused_3[3]; + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Specifies the epoch value with the one that was specified by the + * firmware in the error_report_doorbell_drop_threshold async event + * corresponding to the specific recovery cycle. + */ + uint32_t epoch; + /* The epoch value. */ + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_MASK \ + UINT32_C(0xffffff) + #define HWRM_FUNC_DBR_RECOVERY_COMPLETED_INPUT_EPOCH_VALUE_SFT 0 + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_dbr_recovery_completed_output (size:128b/16B) */ +struct hwrm_func_dbr_recovery_completed_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' * to indicate that the output has been completely written. - * When writing a command completion or response to an internal processor, - * the order of writes has to be such that this field is written last. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. */ uint8_t valid; } __rte_packed; -/********************** - * hwrm_func_vlan_cfg * - **********************/ +/*********************** + * hwrm_func_synce_cfg * + ***********************/ -/* hwrm_func_vlan_cfg_input (size:384b/48B) */ -struct hwrm_func_vlan_cfg_input { +/* hwrm_func_synce_cfg_input (size:192b/24B) */ +struct hwrm_func_synce_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t enables; + /* + * This bit must be '1' for the freq_profile field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_FREQ_PROFILE \ + UINT32_C(0x1) + /* + * This bit must be '1' for the primary_clock_state field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_PRIMARY_CLOCK \ + UINT32_C(0x2) + /* + * This bit must be '1' for the secondary_clock_state field to be + * configured. + */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_ENABLES_SECONDARY_CLOCK \ + UINT32_C(0x4) + /* Frequency profile for SyncE recovered clock. */ + uint8_t freq_profile; + /* Invalid frequency profile */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_INVALID UINT32_C(0x0) + /* 25MHz SyncE clock profile */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_FREQ_PROFILE_25MHZ + /* + * Enable or disable primary clock for PF/port, overriding previous + * primary clock setting. + */ + uint8_t primary_clock_state; + /* Disable clock */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_DISABLE \ + UINT32_C(0x0) + /* Enable clock */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE \ + UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_PRIMARY_CLOCK_STATE_ENABLE + /* + * Enable or disable secondary clock for PF/port, overriding previous + * secondary clock setting. + */ + uint8_t secondary_clock_state; + /* Clock disabled */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_DISABLE \ + UINT32_C(0x0) + /* Clock enabled */ + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE \ + UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_LAST \ + HWRM_FUNC_SYNCE_CFG_INPUT_SECONDARY_CLOCK_STATE_ENABLE + uint8_t unused_0[4]; +} __rte_packed; + +/* hwrm_func_synce_cfg_output (size:128b/16B) */ +struct hwrm_func_synce_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_func_synce_qcfg * + ************************/ + + +/* hwrm_func_synce_qcfg_input (size:192b/24B) */ +struct hwrm_func_synce_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint8_t unused_0[8]; +} __rte_packed; + +/* hwrm_func_synce_qcfg_output (size:128b/16B) */ +struct hwrm_func_synce_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Frequency profile for SyncE recovered clock. */ + uint8_t freq_profile; + /* Invalid frequency profile */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_INVALID UINT32_C(0x0) + /* 25MHz SyncE clock profile */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ UINT32_C(0x1) + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_LAST \ + HWRM_FUNC_SYNCE_QCFG_OUTPUT_FREQ_PROFILE_25MHZ + /* SyncE recovered clock state */ + uint8_t state; + /* + * When this bit is '1', primary clock is enabled for this PF/port. + * When this bit is '0', primary clock is disabled for this PF/port. + */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_PRIMARY_CLOCK_ENABLED \ + UINT32_C(0x1) + /* + * When this bit is '1', secondary clock is enabled for this + * PF/port. + * When this bit is '0', secondary clock is disabled for this + * PF/port. + */ + #define HWRM_FUNC_SYNCE_QCFG_OUTPUT_STATE_SECONDARY_CLOCK_ENABLED \ + UINT32_C(0x2) + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_func_vlan_qcfg * + ***********************/ + + +/* hwrm_func_vlan_qcfg_input (size:192b/24B) */ +struct hwrm_func_vlan_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Function ID of the function that is being + * configured. + * If set to 0xFF... (All Fs), then the configuration is + * for the requesting function. + */ + uint16_t fid; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_func_vlan_qcfg_output (size:320b/40B) */ +struct hwrm_func_vlan_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint64_t unused_0; + /* S-TAG VLAN identifier configured for the function. */ + uint16_t stag_vid; + /* S-TAG PCP value configured for the function. */ + uint8_t stag_pcp; + uint8_t unused_1; + /* + * S-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t stag_tpid; + /* C-TAG VLAN identifier configured for the function. */ + uint16_t ctag_vid; + /* C-TAG PCP value configured for the function. */ + uint8_t ctag_pcp; + uint8_t unused_2; + /* + * C-TAG TPID value configured for the function. This field is specified in + * network byte order. + */ + uint16_t ctag_tpid; + /* Future use. */ + uint32_t rsvd2; + /* Future use. */ + uint32_t rsvd3; + uint8_t unused_3[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_func_vlan_cfg * + **********************/ + + +/* hwrm_func_vlan_cfg_input (size:384b/48B) */ +struct hwrm_func_vlan_cfg_input { /* The HWRM command request type. */ uint16_t req_type; /* @@ -24576,7 +25901,7 @@ struct hwrm_port_phy_qcfg_input { uint8_t unused_0[6]; } __rte_packed; -/* hwrm_port_phy_qcfg_output (size:768b/96B) */ +/* hwrm_port_phy_qcfg_output (size:832b/104B) */ struct hwrm_port_phy_qcfg_output { /* The specific error status for the command. */ uint16_t error_code; @@ -25601,6 +26926,14 @@ struct hwrm_port_phy_qcfg_output { /* 200Gb link speed */ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB \ UINT32_C(0x4) + /* + * This field is used to indicate the reasons for link down. + * This field is set to 0, if the link down reason is unknown. + */ + uint8_t link_down_reason; + /* Remote fault */ + #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_DOWN_REASON_RF UINT32_C(0x1) + uint8_t unused_0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -26934,16 +28267,12 @@ struct hwrm_port_qstats_input { /* Port ID of port that is being queried. */ uint16_t port_id; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for a counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_QSTATS_INPUT_FLAGS_LAST \ - HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0[5]; /* * This is the host address where @@ -27646,16 +28975,12 @@ struct hwrm_port_qstats_ext_input { */ uint16_t rx_stat_size; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for the counter mask, * representing width of each of the stats counters, rather than * counters themselves. */ - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_LAST \ - HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_QSTATS_EXT_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0; /* * This is the host address where @@ -27903,16 +29228,12 @@ struct hwrm_port_ecn_qstats_input { */ uint16_t ecn_stat_buf_size; uint8_t flags; - /* This value is not used to avoid backward compatibility issues. */ - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_UNUSED UINT32_C(0x0) /* * This bit is set to 1 when request is for a counter mask, * representing the width of each of the stats counters, rather * than counters themselves. */ - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) - #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_LAST \ - HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK + #define HWRM_PORT_ECN_QSTATS_INPUT_FLAGS_COUNTER_MASK UINT32_C(0x1) uint8_t unused_0[3]; /* * This is the host address where @@ -28398,6 +29719,12 @@ struct hwrm_port_phy_qcaps_output { */ #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED \ UINT32_C(0x2) + /* + * If set to 1, then this field indicates that + * bank based addressing is supported in firmware. + */ + #define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED \ + UINT32_C(0x4) /* * Number of internal ports for this device. This field allows the FW * to advertise how many internal ports are present. Manufacturing @@ -29720,6 +31047,14 @@ struct hwrm_port_prbs_test_input { #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5) /* PRBS58 */ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6) + /* PRBS49 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS49 UINT32_C(0x7) + /* PRBS10 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS10 UINT32_C(0x8) + /* PRBS20 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS20 UINT32_C(0x9) + /* PRBS13 */ + #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS13 UINT32_C(0xa) /* Invalid */ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff) #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \ @@ -29749,6 +31084,15 @@ struct hwrm_port_prbs_test_input { */ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \ UINT32_C(0x4) + /* If set to 1, FEC stat t-code 0-7 registers are enabled. */ + #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T0_T7 \ + UINT32_C(0x8) + /* + * If set to 1, FEC stat t-code 8-15 registers are enabled. + * If fec_stat_t0_t7 is set, fec_stat_t8_t15 field will be ignored. + */ + #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_FEC_STAT_T8_T15 \ + UINT32_C(0x10) /* Duration in seconds to run the PRBS test. */ uint16_t timeout; /* @@ -29777,7 +31121,15 @@ struct hwrm_port_prbs_test_output { uint16_t resp_len; /* Total length of stored data. */ uint16_t total_data_len; - uint16_t unused_0; + /* This field is used in Output records to indicate the output format */ + uint8_t ber_format; + /* BER_FORMAT_PRBS */ + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_PRBS UINT32_C(0x0) + /* BER_FORMAT_FEC */ + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC UINT32_C(0x1) + #define HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_LAST \ + HWRM_PORT_PRBS_TEST_OUTPUT_BER_FORMAT_FEC + uint8_t unused_0; uint8_t unused_1[3]; /* * This field is used in Output records to indicate that the output @@ -30800,6 +32152,160 @@ struct hwrm_port_ep_tx_qcfg_output { uint8_t valid; } __rte_packed; +/***************** + * hwrm_port_cfg * + *****************/ + + +/* hwrm_port_cfg_input (size:256b/32B) */ +struct hwrm_port_cfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + uint32_t flags; + uint32_t enables; + /* + * This bit must be '1' for the tx_rate_limit field to + * be configured. + */ + #define HWRM_PORT_CFG_INPUT_ENABLES_TX_RATE_LIMIT UINT32_C(0x1) + /* Port ID of port that is to be configured. */ + uint16_t port_id; + uint16_t unused_0; + /* + * Requested setting of TX rate limit in Mbps. + * tx_rate_limit = 0 will cancel the rate limit if any. + * This field is valid only when tx_rate_limit bit in 'enables' + * field is '1'. + */ + uint32_t tx_rate_limit; +} __rte_packed; + +/* hwrm_port_cfg_output (size:128b/16B) */ +struct hwrm_port_cfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint8_t unused_0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************** + * hwrm_port_qcfg * + ******************/ + + +/* hwrm_port_qcfg_input (size:192b/24B) */ +struct hwrm_port_qcfg_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Port ID of port that is to be queried. */ + uint16_t port_id; + uint8_t unused_0[6]; +} __rte_packed; + +/* hwrm_port_qcfg_output (size:192b/24B) */ +struct hwrm_port_qcfg_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + uint32_t supported; + /* + * If set to '1', then this bit indicates that TX rate limit + * could be configured via hwrm_port_cfg command. + */ + #define HWRM_PORT_QCFG_OUTPUT_SUPPORTED_TX_RATE_LIMIT UINT32_C(0x1) + uint32_t enabled; + /* + * If set to '1', then this bit indicates that TX rate limit + * is enabled and could be found in tx_rate_limit field. + */ + #define HWRM_PORT_QCFG_OUTPUT_ENABLED_TX_RATE_LIMIT UINT32_C(0x1) + /* + * Current setting of TX rate limit in Mbps. + * This field is valid only when tx_rate_limit bit in 'enabled' + * field is '1'. + */ + uint32_t tx_rate_limit; + uint8_t unused_0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal processor, + * the order of writes has to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + /*********************** * hwrm_queue_qportcfg * ***********************/ @@ -35688,29 +37194,19 @@ struct hwrm_vnic_update_input { HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP /* * The metadata format type used in all the RX packet completions - * going through this VNIC. + * going through this VNIC. This value is product specific. Refer to + * the L2 HSI completion ring structures for the detailed + * descriptions. For Thor and Thor2, it corresponds to “meta_format” + * in “rx_pkt_cmpl_hi” and “rx_pkt_v3_cmpl_hi”, respectively. */ uint8_t metadata_format_type; - /* No metadata information. */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \ - UINT32_C(0x0) - /* - * Action record pointer (table_scope[4:0], act_rec_ptr[25:0], - * vtag[19:0]). - */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \ - UINT32_C(0x1) - /* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \ - UINT32_C(0x2) - /* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \ - UINT32_C(0x3) - /* Header offsets (hdr_offsets[31:0], vtag[19:0]) */ - #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \ - UINT32_C(0x4) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) #define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \ - HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS + HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_4 /* * The maximum receive unit of the vnic. * Each vnic is associated with a function. @@ -35911,6 +37407,12 @@ struct hwrm_vnic_cfg_input { */ #define HWRM_VNIC_CFG_INPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \ UINT32_C(0x40) + /* + * When this bit is '1' it enables ring selection using the incoming + * spif and lcos for the packet. + */ + #define HWRM_VNIC_CFG_INPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x80) uint32_t enables; /* * This bit must be '1' for the dflt_ring_grp field to be @@ -36259,6 +37761,9 @@ struct hwrm_vnic_qcfg_output { */ #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \ UINT32_C(0x80) + /* When this bit is '1' it indicates port cos_mapping_mode enabled. */ + #define HWRM_VNIC_QCFG_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x100) /* * When returned with a valid CoS Queue id, the CoS Queue/VNIC association * is valid. Otherwise it will return 0xFFFF to indicate no VNIC/CoS @@ -36315,7 +37820,30 @@ struct hwrm_vnic_qcfg_output { #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED UINT32_C(0x2) #define HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_LAST \ HWRM_VNIC_QCFG_OUTPUT_L2_CQE_MODE_MIXED - uint8_t unused_1[3]; + /* + * This field conveys the metadata format type that has been + * configured. This value is product specific. Refer to the L2 HSI + * completion ring structures for the detailed descriptions. For Thor + * and Thor2, it corresponds to “meta_format” in “rx_pkt_cmpl_hi” and + * “rx_pkt_v3_cmpl_hi”, respectively. + */ + uint8_t metadata_format_type; + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_0 UINT32_C(0x0) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_1 UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_2 UINT32_C(0x2) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_3 UINT32_C(0x3) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 UINT32_C(0x4) + #define HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_METADATA_FORMAT_TYPE_4 + /* This field conveys the VNIC operation state. */ + uint8_t vnic_state; + /* Normal operation state. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_NORMAL UINT32_C(0x0) + /* Drop all packets. */ + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP UINT32_C(0x1) + #define HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_LAST \ + HWRM_VNIC_QCFG_OUTPUT_VNIC_STATE_DROP + uint8_t unused_1; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -36557,6 +38085,53 @@ struct hwrm_vnic_qcaps_output { */ #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_L2_CQE_MODE_CAP \ UINT32_C(0x100000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP \ + UINT32_C(0x200000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv4 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP \ + UINT32_C(0x400000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC AH SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP \ + UINT32_C(0x800000) + /* + * When this bit is '1' HW supports hash calculation + * based on IPv6 IPSEC ESP SPI field. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP \ + UINT32_C(0x1000000) + /* + * When outermost_rss_cap is '1' and this bit is '1', the outermost + * RSS hash mode may be set on a PF or trusted VF. + * When outermost_rss_cap is '1' and this bit is '0', the outermost + * RSS hash mode may be set on a PF. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP \ + UINT32_C(0x2000000) + /* + * When this bit is '1' it indicates HW is capable of enabling ring + * selection using the incoming spif and lcos for the packet. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_PORTCOS_MAPPING_MODE \ + UINT32_C(0x4000000) + /* + * When this bit is '1', it indicates controller enabled + * RSS profile TCAM mode. + */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RSS_PROF_TCAM_MODE_ENABLED \ + UINT32_C(0x8000000) + /* When this bit is '1' FW supports VNIC hash mode. */ + #define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_RSS_HASH_MODE_CAP \ + UINT32_C(0x10000000) /* * This field advertises the maximum concurrent TPA aggregations * supported by the VNIC on new devices that support TPA v2 or v3. @@ -36869,6 +38444,38 @@ struct hwrm_vnic_rss_cfg_input { */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6_FLOW_LABEL \ UINT32_C(0x40) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv4_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV4 \ + UINT32_C(0x80) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv4_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV4 \ + UINT32_C(0x100) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_ah_spi_ipv6_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_AH_SPI_IPV6 \ + UINT32_C(0x200) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. Host drivers should set this bit based on + * rss_ipsec_esp_spi_ipv6_cap. + */ + #define HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_ESP_SPI_IPV6 \ + UINT32_C(0x400) /* VNIC ID of VNIC associated with RSS table being configured. */ uint16_t vnic_id; /* @@ -36876,11 +38483,25 @@ struct hwrm_vnic_rss_cfg_input { * Valid values range from 0 to 7. */ uint8_t ring_table_pair_index; - /* Flags to specify different RSS hash modes. */ + /* + * Flags to specify different RSS hash modes. Global RSS hash mode is + * indicated when vnic_id and rss_ctx_idx fields are set to value of + * 0xffff. Only PF can initiate global RSS hash mode setting changes. + * VNIC RSS hash mode is indicated with valid vnic_id and rss_ctx_idx, + * if FW is VNIC_RSS_HASH_MODE capable. FW configures the mode based + * on first come first serve order. Global RSS hash mode and VNIC RSS + * hash modes are mutually exclusive. FW returns invalid error + * if FW receives conflicting requests. To change the current hash + * mode, the mode associated drivers need to be unloaded and apply + * the new configuration. + */ uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * innermost_4 and innermost_2 hash modes are used to configure + * the tuple mode. When this bit is '1' and FW is not + * VNIC_RSS_HASH_MODE capable, It indicates using current RSS hash + * mode setting configured in the device otherwise. */ #define HWRM_VNIC_RSS_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) @@ -37063,9 +38684,17 @@ struct hwrm_vnic_rss_qcfg_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Index to the rss indirection table. */ + /* + * Index to the rss indirection table. This field is used as a lookup + * for chips before Thor - i.e. Cumulus and Whitney. + */ uint16_t rss_ctx_idx; - uint8_t unused_0[6]; + /* + * VNIC ID of VNIC associated with RSS table being queried. This field + * is used as a lookup for Thor and later chips. + */ + uint16_t vnic_id; + uint8_t unused_0[4]; } __rte_packed; /* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ @@ -37084,45 +38713,104 @@ struct hwrm_vnic_rss_qcfg_output { * over source and destination IPv4 addresses of IPv4 * packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 UINT32_C(0x1) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV4 \ + UINT32_C(0x1) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of TCP/IPv4 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 UINT32_C(0x2) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4 \ + UINT32_C(0x2) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv4 addresses and * source/destination ports of UDP/IPv4 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 UINT32_C(0x4) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4 \ + UINT32_C(0x4) /* * When this bit is '1', the RSS hash shall be computed * over source and destination IPv6 addresses of IPv6 * packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 UINT32_C(0x8) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6 \ + UINT32_C(0x8) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of TCP/IPv6 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 UINT32_C(0x10) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6 \ + UINT32_C(0x10) /* * When this bit is '1', the RSS hash shall be computed * over source/destination IPv6 addresses and * source/destination ports of UDP/IPv6 packets. */ - #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 UINT32_C(0x20) + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6 \ + UINT32_C(0x20) + /* + * When this bit is '1', the RSS hash shall be computed + * over source, destination IPv6 addresses and flow label of IPv6 + * packets. Hash type ipv6 and ipv6_flow_label are mutually + * exclusive. HW does not include the flow_label in hash + * calculation for the packets that are matching tcp_ipv6 and + * udp_ipv6 hash types. This bit will be '0' if + * rss_ipv6_flow_label_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_IPV6_FLOW_LABEL \ + UINT32_C(0x40) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv4 packets. This bit will be '0' if rss_ipsec_ah_spi_ipv4_cap + * is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV4 \ + UINT32_C(0x80) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv4 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv4 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv4_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV4 \ + UINT32_C(0x100) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC AH SPI field of IPSEC + * AH/IPv6 packets. This bit will be '0' if + * rss_ipsec_ah_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_AH_SPI_IPV6 \ + UINT32_C(0x200) + /* + * When this bit is '1', the RSS hash shall be computed over + * source/destination IPv6 addresses and IPSEC ESP SPI field of IPSEC + * ESP/IPv6 packets. This bit will be '0' if + * rss_ipsec_esp_spi_ipv6_cap is '0'. + */ + #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_TYPE_ESP_SPI_IPV6 \ + UINT32_C(0x400) uint8_t unused_0[4]; /* This is the value of rss hash key */ uint32_t hash_key[10]; - /* Flags to specify different RSS hash modes. */ + /* + * Flags to specify different RSS hash modes. Setting rss_ctx_idx to + * the value of 0xffff implies a global RSS configuration query. + * hash_mode_flags are only valid for global RSS configuration query. + * Only the PF can initiate a global RSS configuration query. + * The query request fails if any VNIC is configured with hash mode + * and rss_ctx_idx is 0xffff. + */ uint8_t hash_mode_flags; /* - * When this bit is '1', it indicates using current RSS - * hash mode setting configured in the device. + * When this bit is '1' and FW is VNIC_RSS_HASH_MODE capable, + * it indicates VNIC's configured RSS hash mode. + * When this bit is '1' and FW is not VNIC_RSS_HASH_MODE capable, + * It indicates using current RSS hash mode setting configured in the + * device. */ #define HWRM_VNIC_RSS_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \ UINT32_C(0x1) @@ -37832,6 +39520,27 @@ struct hwrm_ring_alloc_input { */ #define HWRM_RING_ALLOC_INPUT_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION \ UINT32_C(0x2) + /* + * Used with enhanced Doorbell Pacing feature, when set to '1' + * this flag indicates that the NQ id that's allocated should be + * used for DBR pacing notifications. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_NQ_DBR_PACING \ + UINT32_C(0x4) + /* + * Host driver should set this flag bit to '1' to enable + * two-completion TX packet timestamp feature. By enabling this + * per QP flag and enabling stamp bit in TX BD lflags, host drivers + * expect two completions, one for regular TX completion and the + * other completion with timestamp. For a QP with both completion + * coalescing and timestamp completion features enabled, completion + * coalescing takes place on regular TX completions. The timestamp + * completions are not coalesced and a separate timestamp completion + * is generated for each packet with stamp bit set in the TX BD + * lflags. + */ + #define HWRM_RING_ALLOC_INPUT_FLAGS_TX_PKT_TS_CMPL_ENABLE \ + UINT32_C(0x8) /* * This value is a pointer to the page table for the * Ring. @@ -38026,7 +39735,7 @@ struct hwrm_ring_alloc_input { * completion rings are allowed. */ uint8_t int_mode; - /* Legacy INTA */ + /* Legacy INTA (deprecated) */ #define HWRM_RING_ALLOC_INPUT_INT_MODE_LEGACY UINT32_C(0x0) /* Reserved */ #define HWRM_RING_ALLOC_INPUT_INT_MODE_RSVD UINT32_C(0x1) @@ -40371,6 +42080,9 @@ struct hwrm_cfa_l2_filter_alloc_input { */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41239,6 +42951,9 @@ struct hwrm_cfa_tunnel_filter_alloc_input { */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41507,6 +43222,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41629,6 +43347,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41743,6 +43464,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_input { */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -41978,8 +43702,11 @@ struct hwrm_cfa_encap_record_alloc_input { */ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \ - HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 + HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE uint8_t unused_0[3]; /* This value is encap data used for the given encap type. */ uint32_t encap_data[20]; @@ -42309,6 +44036,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input { * Applies to UDP and TCP traffic. * 6 - TCP * 17 - UDP + * 1 - ICMP + * 58 - ICMPV6 + * 255 - RSVD */ uint8_t ip_protocol; /* invalid */ @@ -42320,8 +44050,17 @@ struct hwrm_cfa_ntuple_filter_alloc_input { /* UDP */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \ UINT32_C(0x11) + /* ICMP */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMP \ + UINT32_C(0x1) + /* ICMPV6 */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_ICMPV6 \ + UINT32_C(0x3a) + /* RSVD */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD \ + UINT32_C(0xff) #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \ - HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP + HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_IP_PROTOCOL_RSVD /* * If set, this value shall represent the * Logical VNIC ID of the destination VNIC for the RX @@ -42388,6 +44127,9 @@ struct hwrm_cfa_ntuple_filter_alloc_input { */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -42979,6 +44721,9 @@ struct hwrm_cfa_em_flow_alloc_input { */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -44444,6 +46189,9 @@ struct hwrm_cfa_decap_filter_alloc_input { */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -44929,6 +46677,9 @@ struct hwrm_cfa_flow_alloc_input { */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -45182,8 +46933,11 @@ struct hwrm_cfa_flow_action_data { * (IPV6oVXLANGPE) */ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \ - HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 + HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE uint8_t unused[7]; /* This value is encap data for the associated encap type. */ uint32_t encap_data[20]; @@ -45238,6 +46992,9 @@ struct hwrm_cfa_flow_tunnel_hdr_data { */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) /* Any tunneled traffic */ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \ UINT32_C(0xff) @@ -45377,19 +47134,35 @@ struct hwrm_cfa_flow_info_input { /* Max flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \ UINT32_C(0xfff) - #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0 /* CNP flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \ UINT32_C(0x1000) /* RoCEv1 flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \ UINT32_C(0x2000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_TX \ + UINT32_C(0x3000) /* RoCEv2 flow handle */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \ UINT32_C(0x4000) /* Direction rx = 1 */ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \ UINT32_C(0x8000) + /* CNP flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT_RX \ + UINT32_C(0x9000) + /* RoCEv1 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT_RX \ + UINT32_C(0xa000) + /* NIC flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_NIC_RX \ + UINT32_C(0xb000) + /* RoCEv2 flow handle */ + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX \ + UINT32_C(0xc000) + #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_LAST \ + HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT_RX uint8_t unused_0[6]; /* This value identifies a set of CFA data structures used for a flow. */ uint64_t ext_flow_handle; @@ -45629,27 +47402,67 @@ struct hwrm_cfa_flow_stats_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Flow handle. */ + /* Number of valid flows in this command. */ uint16_t num_flows; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_0 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_0; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_1 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_1; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_2 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_2; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_3 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_3; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_4 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_4; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_5 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_5; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_6 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_6; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_7 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_7; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_8 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_8; - /* Flow handle. */ + /* + * Flow handle. + * For a listing of applicable flow_handle_9 values, see enumeration + * in hwrm_cfa_flow_info_input. + */ uint16_t flow_handle_9; uint8_t unused_0[2]; /* Flow ID of a flow. */ @@ -45724,7 +47537,16 @@ struct hwrm_cfa_flow_stats_output { uint64_t byte_8; /* byte_9 is 64 b */ uint64_t byte_9; - uint8_t unused_0[7]; + /* + * If a flow has been hit, the bit representing the flow will be 1. + * Likewise, if a flow has not, the bit representing the flow + * will be 0. Mapping will match flow numbers where bitX is for flowX + * (ex: bit 0 is flow0). This only applies for NIC flows. Upon + * reading of the flow, the bit will be cleared for the flow and only + * set again when traffic is received by the flow. + */ + uint16_t flow_hits; + uint8_t unused_0[5]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -46498,27 +48320,36 @@ struct hwrm_cfa_pair_alloc_input { * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ uint16_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_VF2FN \ UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN \ UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2REP \ UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PROXY \ UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_PFPAIR \ UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. */ + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \ UINT32_C(0x5) /* * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. + * to new PF. (deprecated) */ #define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \ UINT32_C(0x6) @@ -46672,21 +48503,30 @@ struct hwrm_cfa_pair_free_input { * 5-rep2fn_mod, 6-rep2fn_modall, 7-rep2fn_truflow). */ uint16_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) - /* Modify existing rep2fn pair and move pair to new PF. */ + /* Modify existing rep2fn pair and move pair to new PF. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD UINT32_C(0x5) /* * Modify existing rep2fn pairs paired with same PF and move pairs - * to new PF. + * to new PF. (deprecated) */ #define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL UINT32_C(0x6) /* @@ -46808,15 +48648,24 @@ struct hwrm_cfa_pair_info_output { uint16_t tx_cfa_action_b; /* Pair mode (0-vf2fn, 1-rep2fn, 2-rep2rep, 3-proxy, 4-pfpair). */ uint8_t pair_mode; - /* Pair between VF on local host with PF or VF on specified host. */ + /* + * Pair between VF on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_VF2FN UINT32_C(0x0) - /* Pair between REP on local host with PF or VF on specified host. */ + /* + * Pair between REP on local host with PF or VF on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2FN UINT32_C(0x1) - /* Pair between REP on local host with REP on specified host. */ + /* + * Pair between REP on local host with REP on specified host. + * (deprecated) + */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_REP2REP UINT32_C(0x2) - /* Pair for the proxy interface. */ + /* Pair for the proxy interface. (deprecated) */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PROXY UINT32_C(0x3) - /* Pair for the PF interface. */ + /* Pair for the PF interface. (deprecated) */ #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR UINT32_C(0x4) #define HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_LAST \ HWRM_CFA_PAIR_INFO_OUTPUT_PAIR_MODE_PFPAIR @@ -47084,6 +48933,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output { */ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \ UINT32_C(0x2000) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE \ + UINT32_C(0x4000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -48272,7 +50124,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * Value of 1 to indicate firmware support flow batch delete * operation through HWRM_CFA_FLOW_FLUSH command. * Value of 0 to indicate that the firmware does not support flow - * batch delete operation. + * batch delete operation. (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \ UINT32_C(0x4) @@ -48280,7 +50132,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * Value of 1 to indicate that the firmware support flow reset all * operation through HWRM_CFA_FLOW_FLUSH command. * Value of 0 indicates firmware does not support flow reset all - * operation. + * operation. (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \ UINT32_C(0x8) @@ -48295,12 +50147,14 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { /* * Value of 1 to indicate that firmware supports TX EEM flows. * Value of 0 indicates firmware does not support TX EEM flows. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \ UINT32_C(0x20) /* * Value of 1 to indicate that firmware supports RX EEM flows. * Value of 0 indicates firmware does not support RX EEM flows. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \ UINT32_C(0x40) @@ -48309,6 +50163,7 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { * allocation of an on-chip flow counter which can be used for EEM * flows. Value of 0 indicates firmware does not support the dynamic * allocation of an on-chip flow counter. + * (deprecated) */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \ UINT32_C(0x80) @@ -48390,6 +50245,19 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output { */ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED \ UINT32_C(0x40000) + /* + * If set to 1, firmware is capable returning stats for nic flows + * in cfa_flow_stats command where flow_handle value 0xF000. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NIC_FLOW_STATS_SUPPORTED \ + UINT32_C(0x80000) + /* + * If set to 1, firmware is capable of supporting these additional + * ip_protoccols: ICMP, ICMPV6, RSVD for ntuple rules. By default, + * this flag should be 0 for older version of firmware. + */ + #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED \ + UINT32_C(0x100000) uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output @@ -50172,7 +52040,7 @@ struct hwrm_tf_tbl_type_get_input { uint32_t index; } __rte_packed; -/* hwrm_tf_tbl_type_get_output (size:1216b/152B) */ +/* hwrm_tf_tbl_type_get_output (size:2240b/280B) */ struct hwrm_tf_tbl_type_get_output { /* The specific error status for the command. */ uint16_t error_code; @@ -50189,7 +52057,7 @@ struct hwrm_tf_tbl_type_get_output { /* unused */ uint16_t unused0; /* Response data. */ - uint8_t data[128]; + uint8_t data[256]; /* unused */ uint8_t unused1[7]; /* @@ -50250,6 +52118,8 @@ struct hwrm_tf_tbl_type_set_input { #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_LAST \ HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DIR_TX + /* Indicate table data is being sent via DMA. */ + #define HWRM_TF_TBL_TYPE_SET_INPUT_FLAGS_DMA UINT32_C(0x2) /* unused. */ uint8_t unused0[2]; /* @@ -52298,133 +54168,2494 @@ struct hwrm_tf_if_tbl_set_input { * point to a physically contiguous block of memory. */ uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Index of the type to set. */ + uint32_t index; + /* Size of the data to set. */ + uint16_t size; + /* unused */ + uint8_t unused1[6]; + /* Data to be set. */ + uint8_t data[88]; +} __rte_packed; + +/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ +struct hwrm_tf_if_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tf_tbl_type_bulk_get * + *****************************/ + + +/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ +struct hwrm_tf_tbl_type_bulk_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entries on read. + */ + #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) + /* unused. */ + uint8_t unused0[2]; + /* + * Type of the resource, defined globally in the + * hwrm_tf_resc_type enum. + */ + uint32_t type; + /* Starting index of the type to retrieve. */ + uint32_t start_index; + /* Number of entries to retrieve. */ + uint32_t num_entries; + /* Number of entries to retrieve. */ + uint32_t unused1; + /* Host memory where data will be stored. */ + uint64_t host_addr; +} __rte_packed; + +/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ +struct hwrm_tf_tbl_type_bulk_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Response code. */ + uint32_t resp_code; + /* Response size. */ + uint16_t size; + /* unused */ + uint8_t unused0; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_tf_session_hotup_state_set * + ***********************************/ + + +/* hwrm_tf_session_hotup_state_set_input (size:192b/24B) */ +struct hwrm_tf_session_hotup_state_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Shared session state. */ + uint16_t state; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_HOTUP_STATE_SET_INPUT_FLAGS_DIR_TX +} __rte_packed; + +/* hwrm_tf_session_hotup_state_set_output (size:128b/16B) */ +struct hwrm_tf_session_hotup_state_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************************** + * hwrm_tf_session_hotup_state_get * + ***********************************/ + + +/* hwrm_tf_session_hotup_state_get_input (size:192b/24B) */ +struct hwrm_tf_session_hotup_state_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint32_t fw_session_id; + /* Control flags. */ + uint16_t flags; + /* Indicates the flow direction. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TF_SESSION_HOTUP_STATE_GET_INPUT_FLAGS_DIR_TX + /* unused. */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tf_session_hotup_state_get_output (size:128b/16B) */ +struct hwrm_tf_session_hotup_state_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Shared session HA state. */ + uint16_t state; + /* Shared session HA reference count. */ + uint16_t ref_cnt; + /* unused. */ + uint8_t unused0[3]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_tbl_scope_qcaps * + ****************************/ + + +/* + * TruFlow command to check if firmware is capable of + * supporting table scopes. + */ +/* hwrm_tfc_tbl_scope_qcaps_input (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_qcaps_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_qcaps_output (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_qcaps_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * The maximum number of lookup records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_lkup_rec_cnt; + /* + * The maximum number of action records that a table scope can support. + * This field is only valid if tbl_scope_capable is not zero. + */ + uint32_t max_act_rec_cnt; + /* Not zero if firmware capable of table scopes. */ + uint8_t tbl_scope_capable; + /* + * log2 of the number of lookup static buckets that a table scope can + * support. This field is only valid if tbl_scope_capable is not zero. + */ + uint8_t max_lkup_static_buckets_exp; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_tfc_tbl_scope_id_alloc * + *******************************/ + + +/* + * TruFlow command to allocate a table scope ID and create the pools. + * + * There is no corresponding free command since a table scope + * ID will automatically be freed once the last FID is removed. + * That is, when the hwrm_tfc_tbl_scope_fid_rem command returns + * a fid_cnt of 0 that also means that the table scope ID has + * been freed. + */ +/* hwrm_tfc_tbl_scope_id_alloc_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The maximum number of pools for this table scope. */ + uint16_t max_pools; + /* Non-zero if this table scope is shared. */ + uint8_t shared; + /* + * The size of the lookup pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pool_sz_exp[2]; + /* + * The size of the action pools per direction expressed as + * log2(max_records/max_pools). That is, size=2^exp. + * + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pool_sz_exp[2]; + /* unused. */ + uint8_t unused0; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The table scope ID that was allocated. */ + uint8_t tsid; + /* + * Non-zero if this is the first FID associated with this table scope + * ID. + */ + uint8_t first; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tfc_tbl_scope_config * + *****************************/ + + +/* TruFlow command to configure the table scope memory. */ +/* hwrm_tfc_tbl_scope_config_input (size:704b/88B) */ +struct hwrm_tfc_tbl_scope_config_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The base addresses for lookup memory. + * Array is indexed by enum cfa_dir. + */ + uint64_t lkup_base_addr[2]; + /* + * The base addresses for action memory. + * Array is indexed by enum cfa_dir. + */ + uint64_t act_base_addr[2]; + /* + * The number of minimum sized lkup records per direction. + * In this usage, records are the minimum lookup memory + * allocation unit in a table scope. This value is the total + * memory required for buckets and entries. + * + * Array is indexed by enum cfa_dir. + */ + uint32_t lkup_rec_cnt[2]; + /* + * The number of minimum sized action records per direction. + * Similar to the lkup_rec_cnt, records are the minimum + * action memory allocation unit in a table scope. + * + * Array is indexed by enum cfa_dir. + */ + uint32_t act_rec_cnt[2]; + /* + * The number of static lookup buckets in the table scope. + * Array is indexed by enum cfa_dir. + */ + uint32_t lkup_static_bucket_cnt[2]; + /* The page size of the table scope. */ + uint32_t pbl_page_sz; + /* + * The PBL level for lookup memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t lkup_pbl_level[2]; + /* + * The PBL level for action memory. + * Array is indexed by enum cfa_dir. + */ + uint8_t act_pbl_level[2]; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_config_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_config_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************* + * hwrm_tfc_tbl_scope_deconfig * + *******************************/ + + +/* TruFlow command to deconfigure the table scope memory. */ +/* hwrm_tfc_tbl_scope_deconfig_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_deconfig_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_deconfig_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_deconfig_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_tbl_scope_fid_add * + ******************************/ + + +/* TruFlow command to add a FID to a table scope. */ +/* hwrm_tfc_tbl_scope_fid_add_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_fid_add_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_fid_add_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_fid_add_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs currently in the table scope ID. */ + uint8_t fid_cnt; + /* unused. */ + uint8_t unused0[6]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_tbl_scope_fid_rem * + ******************************/ + + +/* TruFlow command to remove a FID from a table scope. */ +/* hwrm_tfc_tbl_scope_fid_rem_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_fid_rem_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* The table scope ID. */ + uint8_t tsid; + /* unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_fid_rem_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_fid_rem_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs remaining in the table scope ID. */ + uint16_t fid_cnt; + /* unused. */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************************* + * hwrm_tfc_tbl_scope_pool_alloc * + *********************************/ + + +/* hwrm_tfc_tbl_scope_pool_alloc_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_pool_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Table Scope ID */ + uint8_t tsid; + /* Control flags. Direction and type. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_DIR_TX + /* Indicates the table type. */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE \ + UINT32_C(0x2) + /* Lookup table */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LOOKUP \ + (UINT32_C(0x0) << 1) + /* Action table */ + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION \ + (UINT32_C(0x1) << 1) + #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_ALLOC_INPUT_FLAGS_TYPE_ACTION + /* Unused */ + uint8_t unused[6]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_pool_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_pool_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Pool ID */ + uint16_t pool_id; + /* Pool size exponent. An exponent of 0 indicates a failure. */ + uint8_t pool_sz_exp; + /* unused. */ + uint8_t unused1[4]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/******************************** + * hwrm_tfc_tbl_scope_pool_free * + ********************************/ + + +/* hwrm_tfc_tbl_scope_pool_free_input (size:192b/24B) */ +struct hwrm_tfc_tbl_scope_pool_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Table Scope ID */ + uint8_t tsid; + /* Control flags. Direction and type. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_DIR_TX + /* Indicates the table type. */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE \ + UINT32_C(0x2) + /* Lookup table */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LOOKUP \ + (UINT32_C(0x0) << 1) + /* Action table */ + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION \ + (UINT32_C(0x1) << 1) + #define HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_LAST \ + HWRM_TFC_TBL_SCOPE_POOL_FREE_INPUT_FLAGS_TYPE_ACTION + /* Pool ID */ + uint16_t pool_id; + /* Unused */ + uint8_t unused[4]; +} __rte_packed; + +/* hwrm_tfc_tbl_scope_pool_free_output (size:128b/16B) */ +struct hwrm_tfc_tbl_scope_pool_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/***************************** + * hwrm_tfc_session_id_alloc * + *****************************/ + + +/* + * Allocate a TFC session. Requests the firmware to allocate a TFC + * session identifier and associate a forwarding function with the + * session. Though there's not an explicit matching free for a session + * id alloc, dis-associating the last fid from a session id (fid_cnt goes + * to 0), will result in this session id being freed automatically. + */ +/* hwrm_tfc_session_id_alloc_input (size:128b/16B) */ +struct hwrm_tfc_session_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; +} __rte_packed; + +/* hwrm_tfc_session_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_session_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_session_fid_add * + ****************************/ + + +/* + * Associate a TFC session id with a forwarding function. The target_fid + * will be associated with the passed in sid. + */ +/* hwrm_tfc_session_fid_add_input (size:192b/24B) */ +struct hwrm_tfc_session_fid_add_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tfc_session_fid_add_output (size:128b/16B) */ +struct hwrm_tfc_session_fid_add_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/**************************** + * hwrm_tfc_session_fid_rem * + ****************************/ + + +/* + * Dis-associate a TFC session from the target_fid. + * Though there's not an explicit matching free for a + * session id alloc, dis-associating the last fid from a session id + * (fid_cnt goes to 0), will result in this session id being freed + * automatically. + */ +/* hwrm_tfc_session_fid_rem_input (size:192b/24B) */ +struct hwrm_tfc_session_fid_rem_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. + */ + uint16_t sid; + /* Unused field */ + uint8_t unused0[6]; +} __rte_packed; + +/* hwrm_tfc_session_fid_rem_output (size:128b/16B) */ +struct hwrm_tfc_session_fid_rem_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The number of FIDs that share this session. */ + uint16_t fid_cnt; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_ident_alloc * + ************************/ + + +/* + * Allocate a TFC identifier. Requests the firmware to + * allocate a TFC identifier. The session id and track_type are passed + * in. The tracking_id is either the sid or target_fid depends on the + * track_type. The resource subtype is passed in, an id corresponding + * to all these is allocated and returned in the HWRM response. + */ +/* hwrm_tfc_ident_alloc_input (size:192b/24B) */ +struct hwrm_tfc_ident_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. Will be used to track this identifier. + */ + uint16_t sid; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDENT_ALLOC_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking tag to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDENT_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused field */ + uint8_t unused0[3]; +} __rte_packed; + +/* hwrm_tfc_ident_alloc_output (size:128b/16B) */ +struct hwrm_tfc_ident_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Resource identifier allocated by the firmware using + * parameters above. + */ + uint16_t ident_id; + /* Unused field */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tfc_ident_free * + ***********************/ + + +/* + * Requests the firmware to free a TFC resource identifier. + * A resource subtype and session id are passed in. + * An identifier (previously allocated) corresponding to all these is + * freed, only after various sanity checks are completed. + */ +/* hwrm_tfc_ident_free_input (size:192b/24B) */ +struct hwrm_tfc_ident_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session identifier for the session created by the + * firmware. Will be used to validate this request. + */ + uint16_t sid; + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Control flags. Direction. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDENT_FREE_INPUT_FLAGS_DIR_TX + /* The resource identifier to be freed */ + uint16_t ident_id; + /* Reserved */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_ident_free_output (size:128b/16B) */ +struct hwrm_tfc_ident_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/************************** + * hwrm_tfc_idx_tbl_alloc * + **************************/ + + +/* hwrm_tfc_idx_tbl_alloc_input (size:192b/24B) */ +struct hwrm_tfc_idx_tbl_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Reserved */ + uint8_t unused0[3]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_alloc_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/****************************** + * hwrm_tfc_idx_tbl_alloc_set * + ******************************/ + + +/* hwrm_tfc_idx_tbl_alloc_set_input (size:1088b/136B) */ +struct hwrm_tfc_idx_tbl_alloc_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data packing does not change. + */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_IDX_TBL_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Reserved */ + uint8_t unused0; + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* The location of the dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[104]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_alloc_set_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_alloc_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_idx_tbl_set * + ************************/ + + +/* hwrm_tfc_idx_tbl_set_input (size:1088b/136B) */ +struct hwrm_tfc_idx_tbl_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DIR_TX + /* + * Indicate device data is being sent via DMA, the device + * data packing does not change. + */ + #define HWRM_TFC_IDX_TBL_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry in bytes. */ + uint16_t data_size; + /* The location of the dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[104]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_set_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************ + * hwrm_tfc_idx_tbl_get * + ************************/ + + +/* hwrm_tfc_idx_tbl_get_input (size:256b/32B) */ +struct hwrm_tfc_idx_tbl_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR \ + UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_RX \ + UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX \ + UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_DIR_TX + /* + * When set use the special access register access to clear + * the table entry on read. + */ + #define HWRM_TFC_IDX_TBL_GET_INPUT_FLAGS_CLEAR_ON_READ \ + UINT32_C(0x2) + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* + * Index table index returned during alloc by the + * firmware. + */ + uint16_t idx_tbl_id; + /* The size of the index table entry buffer in bytes. */ + uint16_t buffer_size; + /* The location of the response dma buffer */ + uint64_t dma_addr; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_get_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The size of the index table buffer returned in device size bytes. */ + uint16_t data_size; + /* unused */ + uint8_t unused1[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/************************* + * hwrm_tfc_idx_tbl_free * + *************************/ + + +/* hwrm_tfc_idx_tbl_free_input (size:192b/24B) */ +struct hwrm_tfc_idx_tbl_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_IDX_TBL_FREE_INPUT_FLAGS_DIR_TX + /* + * CFA resource subtype. For definitions, please see + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Index table id to be freed by the firmware. */ + uint16_t idx_tbl_id; + /* Reserved */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_idx_tbl_free_output (size:128b/16B) */ +struct hwrm_tfc_idx_tbl_free_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Reserved */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/* TruFlow resources request for a global id. */ +/* tfc_global_id_hwrm_req (size:64b/8B) */ +struct tfc_global_id_hwrm_req { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* Number of the type of resources. */ + uint16_t cnt; +} __rte_packed; + +/* The reserved resources for the global id. */ +/* tfc_global_id_hwrm_rsp (size:64b/8B) */ +struct tfc_global_id_hwrm_rsp { + /* Type of the resource, defined in enum cfa_resource_type HCAPI RM. */ + uint16_t rtype; + /* Indicates the flow direction in type of cfa_dir. */ + uint16_t dir; + /* Subtype of the resource type. */ + uint16_t subtype; + /* The global id that the resources reserved for. */ + uint16_t id; +} __rte_packed; + +/**************************** + * hwrm_tfc_global_id_alloc * + ****************************/ + + +/* hwrm_tfc_global_id_alloc_input (size:320b/40B) */ +struct hwrm_tfc_global_id_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ + uint16_t sid; + /* Global domain id. */ + uint16_t global_id; + /* + * Defines the array size of the provided req_addr and + * resv_addr array buffers. Should be set to the number of + * request entries. + */ + uint16_t req_cnt; + /* unused. */ + uint8_t unused0[2]; + /* + * This is the DMA address for the request input data array + * buffer. Array is of tfc_global_id_hwrm_req type. Size of the + * array buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t req_addr; + /* + * This is the DMA address for the resc output data array + * buffer. Array is of tfc_global_id_hwrm_rsp type. Size of the array + * buffer is provided by the 'req_cnt' field in this + * message. + */ + uint64_t resc_addr; +} __rte_packed; + +/* hwrm_tfc_global_id_alloc_output (size:128b/16B) */ +struct hwrm_tfc_global_id_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Size of the returned hwrm_tfc_global_id_req data array. The value + * cannot exceed the req_cnt defined by the input msg. The data + * array is returned using the resv_addr specified DMA + * address also provided by the input msg. + */ + uint16_t rsp_cnt; + /* Non-zero if this is the first allocation for the global ID. */ + uint8_t first; + /* unused. */ + uint8_t unused0[4]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tfc_tcam_set * + *********************/ + + +/* hwrm_tfc_tcam_set_input (size:1088b/136B) */ +struct hwrm_tfc_tcam_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* unused. */ + uint8_t unused0[6]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * TCAM key located at offset 0, mask located at mask_offset + * and result at result_offset for the device. + */ + uint8_t dev_data[96]; +} __rte_packed; + +/* hwrm_tfc_tcam_set_output (size:128b/16B) */ +struct hwrm_tfc_tcam_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* unused. */ + uint8_t unused0[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************* + * hwrm_tfc_tcam_get * + *********************/ + + +/* hwrm_tfc_tcam_get_input (size:192b/24B) */ +struct hwrm_tfc_tcam_get_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_GET_INPUT_FLAGS_DIR_TX + /* + * Subtype of TCAM resource See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Session id associated with the firmware. Will be used + * for validation if the track type matches. + */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* unused. */ + uint8_t unused0[2]; +} __rte_packed; + +/* hwrm_tfc_tcam_get_output (size:2368b/296B) */ +struct hwrm_tfc_tcam_get_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Number of bytes in the TCAM result. */ + uint16_t result_size; + /* unused. */ + uint8_t unused0[4]; + /* + * TCAM key located at offset 0, mask located at key_size + * and result at 2 * key_size for the device. + */ + uint8_t dev_data[272]; + /* unused. */ + uint8_t unused1[7]; + /* + * This field is used in Output records to indicate that the + * output is completely written to RAM. This field should be + * read as '1' to indicate that the output has been + * completely written. When writing a command completion or + * response to an internal processor, the order of writes has + * to be such that this field is written last. + */ + uint8_t valid; +} __rte_packed; + +/*********************** + * hwrm_tfc_tcam_alloc * + ***********************/ + + +/* hwrm_tfc_tcam_alloc_input (size:256b/32B) */ +struct hwrm_tfc_tcam_alloc_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_ALLOC_INPUT_FLAGS_DIR_TX + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_TCAM_ALLOC_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused. */ + uint8_t unused0[7]; +} __rte_packed; + +/* hwrm_tfc_tcam_alloc_output (size:128b/16B) */ +struct hwrm_tfc_tcam_alloc_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* + * Index table entry allocated by the firmware using the + * parameters above. + */ + uint16_t idx; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/*************************** + * hwrm_tfc_tcam_alloc_set * + ***************************/ + + +/* hwrm_tfc_tcam_alloc_set_input (size:1088b/136B) */ +struct hwrm_tfc_tcam_alloc_set_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* Control flags. */ + uint8_t flags; + /* Indicates the flow direction. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + /* If this bit set to 0, then it indicates rx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + /* If this bit is set to 1, then it indicates tx flow. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DIR_TX + /* Indicate device data is being sent via DMA. */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_FLAGS_DMA UINT32_C(0x2) + /* + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. + */ + uint8_t subtype; + /* + * Unique session id for the session created by the + * firmware. Will be used to track this index table entry + * only if track type is track_type_sid. + */ + uint16_t sid; + /* Number of bytes in the TCAM key. */ + uint16_t key_size; + /* The size of the TCAM table entry in bytes. */ + uint16_t result_size; + /* Entry priority. */ + uint16_t priority; + /* Describes the type of tracking id to be used */ + uint8_t track_type; + /* Invalid track type */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_INVALID \ + UINT32_C(0x0) + /* Tracked by session id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_SID \ + UINT32_C(0x1) + /* Tracked by function id */ + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID \ + UINT32_C(0x2) + #define HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_LAST \ + HWRM_TFC_TCAM_ALLOC_SET_INPUT_TRACK_TYPE_TRACK_TYPE_FID + /* Unused */ + uint8_t unused[5]; + /* The location of the response dma buffer */ + uint64_t dma_addr; + /* + * Index table data located at offset 0. If dma bit is set, + * then this field contains the DMA buffer pointer. + */ + uint8_t dev_data[96]; +} __rte_packed; + +/* hwrm_tfc_tcam_alloc_set_output (size:128b/16B) */ +struct hwrm_tfc_tcam_alloc_set_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Reserved */ + uint8_t unused0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field + * is written last. + */ + uint8_t valid; +} __rte_packed; + +/********************** + * hwrm_tfc_tcam_free * + **********************/ + + +/* hwrm_tfc_tcam_free_input (size:192b/24B) */ +struct hwrm_tfc_tcam_free_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; /* Control flags. */ - uint16_t flags; + uint8_t flags; /* Indicates the flow direction. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR UINT32_C(0x1) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR UINT32_C(0x1) /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_RX UINT32_C(0x0) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_RX UINT32_C(0x0) /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX UINT32_C(0x1) - #define HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_IF_TBL_SET_INPUT_FLAGS_DIR_TX - /* unused. */ - uint8_t unused0[2]; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Index of the type to set. */ - uint32_t index; - /* Size of the data to set. */ - uint16_t size; - /* unused */ - uint8_t unused1[6]; - /* Data to be set. */ - uint8_t data[88]; -} __rte_packed; - -/* hwrm_tf_if_tbl_set_output (size:128b/16B) */ -struct hwrm_tf_if_tbl_set_output { - /* The specific error status for the command. */ - uint16_t error_code; - /* The HWRM command request type. */ - uint16_t req_type; - /* The sequence ID from the original command. */ - uint16_t seq_id; - /* The length of the response data in number of bytes. */ - uint16_t resp_len; - /* unused. */ - uint8_t unused0[7]; - /* - * This field is used in Output records to indicate that the output - * is completely written to RAM. This field should be read as '1' - * to indicate that the output has been completely written. - * When writing a command completion or response to an internal - * processor, the order of writes has to be such that this field - * is written last. - */ - uint8_t valid; -} __rte_packed; - -/***************************** - * hwrm_tf_tbl_type_bulk_get * - *****************************/ - - -/* hwrm_tf_tbl_type_bulk_get_input (size:384b/48B) */ -struct hwrm_tf_tbl_type_bulk_get_input { - /* The HWRM command request type. */ - uint16_t req_type; + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX UINT32_C(0x1) + #define HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_LAST \ + HWRM_TFC_TCAM_FREE_INPUT_FLAGS_DIR_TX /* - * The completion ring to send the completion event on. This should - * be the NQ ID returned from the `nq_alloc` HWRM command. + * Subtype of TCAM resource. See + * cfa_v3/include/cfa_resources.h. */ - uint16_t cmpl_ring; + uint8_t subtype; /* - * The sequence ID is used by the driver for tracking multiple - * commands. This ID is treated as opaque data by the firmware and - * the value is returned in the `hwrm_resp_hdr` upon completion. + * Session id associated with the firmware. Will be used + * for validation if the track type matches. */ - uint16_t seq_id; - /* - * The target ID of the command: - * * 0x0-0xFFF8 - The function ID - * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors - * * 0xFFFD - Reserved for user-space HWRM interface - * * 0xFFFF - HWRM - */ - uint16_t target_id; - /* - * A physical address pointer pointing to a host buffer that the - * command's response data will be written. This can be either a host - * physical address (HPA) or a guest physical address (GPA) and must - * point to a physically contiguous block of memory. - */ - uint64_t resp_addr; - /* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */ - uint32_t fw_session_id; - /* Control flags. */ - uint16_t flags; - /* Indicates the flow direction. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR \ - UINT32_C(0x1) - /* If this bit set to 0, then it indicates rx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_RX \ - UINT32_C(0x0) - /* If this bit is set to 1, then it indicates tx flow. */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX \ - UINT32_C(0x1) - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_LAST \ - HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_DIR_TX - /* - * When set use the special access register access to clear - * the table entries on read. - */ - #define HWRM_TF_TBL_TYPE_BULK_GET_INPUT_FLAGS_CLEAR_ON_READ \ - UINT32_C(0x2) - /* unused. */ + uint16_t sid; + /* Logical TCAM ID. */ + uint16_t tcam_id; + /* Reserved */ uint8_t unused0[2]; - /* - * Type of the resource, defined globally in the - * hwrm_tf_resc_type enum. - */ - uint32_t type; - /* Starting index of the type to retrieve. */ - uint32_t start_index; - /* Number of entries to retrieve. */ - uint32_t num_entries; - /* Number of entries to retrieve. */ - uint32_t unused1; - /* Host memory where data will be stored. */ - uint64_t host_addr; } __rte_packed; -/* hwrm_tf_tbl_type_bulk_get_output (size:128b/16B) */ -struct hwrm_tf_tbl_type_bulk_get_output { +/* hwrm_tfc_tcam_free_output (size:128b/16B) */ +struct hwrm_tfc_tcam_free_output { /* The specific error status for the command. */ uint16_t error_code; /* The HWRM command request type. */ @@ -52433,12 +56664,8 @@ struct hwrm_tf_tbl_type_bulk_get_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - /* Response code. */ - uint32_t resp_code; - /* Response size. */ - uint16_t size; - /* unused */ - uint8_t unused0; + /* Reserved */ + uint8_t unused0[7]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52505,8 +56732,20 @@ struct hwrm_tunnel_dst_port_query_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0[7]; } __rte_packed; @@ -52538,7 +56777,38 @@ struct hwrm_tunnel_dst_port_query_output { * configured. */ uint16_t tunnel_dst_port_val; - uint8_t unused_0[3]; + /* + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 + */ + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR0 \ + UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR1 \ + UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR2 \ + UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR3 \ + UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR4 \ + UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR5 \ + UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR6 \ + UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_QUERY_OUTPUT_UPAR_IN_USE_UPAR7 \ + UINT32_C(0x80) + uint8_t unused_0[2]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52604,8 +56874,20 @@ struct hwrm_tunnel_dst_port_alloc_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0; /* * This field represents the value of L4 destination port used @@ -52636,7 +56918,51 @@ struct hwrm_tunnel_dst_port_alloc_output { * types that has l4 destination port parameters. */ uint16_t tunnel_dst_port_id; - uint8_t unused_0[5]; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_SUCCESS \ + UINT32_C(0x0) + /* Tunnel port is already allocated */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_ALLOCATED \ + UINT32_C(0x1) + /* Out of resources error */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE \ + UINT32_C(0x2) + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_LAST \ + HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_ERROR_INFO_ERR_NO_RESOURCE + /* + * This field represents the UPAR usage status. + * Available UPARs on wh+ are UPAR0 and UPAR1 + * Available UPARs on Thor are UPAR0 to UPAR3 + * Available UPARs on Thor2 are UPAR0 to UPAR7 + */ + uint8_t upar_in_use; + /* This bit will be '1' when UPAR0 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR0 \ + UINT32_C(0x1) + /* This bit will be '1' when UPAR1 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR1 \ + UINT32_C(0x2) + /* This bit will be '1' when UPAR2 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR2 \ + UINT32_C(0x4) + /* This bit will be '1' when UPAR3 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR3 \ + UINT32_C(0x8) + /* This bit will be '1' when UPAR4 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR4 \ + UINT32_C(0x10) + /* This bit will be '1' when UPAR5 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR5 \ + UINT32_C(0x20) + /* This bit will be '1' when UPAR6 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR6 \ + UINT32_C(0x40) + /* This bit will be '1' when UPAR7 is IN_USE */ + #define HWRM_TUNNEL_DST_PORT_ALLOC_OUTPUT_UPAR_IN_USE_UPAR7 \ + UINT32_C(0x80) + uint8_t unused_0[3]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -52702,8 +57028,20 @@ struct hwrm_tunnel_dst_port_free_input { /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \ UINT32_C(0xc) + /* Custom GRE uses UPAR to parse customized GRE packets. This is not supported. */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_CUSTOM_GRE \ + UINT32_C(0xd) + /* Enhanced Common Packet Radio Interface (eCPRI) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_ECPRI \ + UINT32_C(0xe) + /* IPv6 Segment Routing (SRv6) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_SRV6 \ + UINT32_C(0xf) + /* Generic Protocol Extension for VXLAN (VXLAN-GPE) */ + #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE \ + UINT32_C(0x10) #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \ - HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 + HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE uint8_t unused_0; /* * Identifier of a tunnel L4 destination port value. Only applies to tunnel @@ -52723,7 +57061,20 @@ struct hwrm_tunnel_dst_port_free_output { uint16_t seq_id; /* The length of the response data in number of bytes. */ uint16_t resp_len; - uint8_t unused_1[7]; + /* Error information */ + uint8_t error_info; + /* No error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_SUCCESS \ + UINT32_C(0x0) + /* Not owner error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_OWNER \ + UINT32_C(0x1) + /* Not allocated error */ + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED \ + UINT32_C(0x2) + #define HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_LAST \ + HWRM_TUNNEL_DST_PORT_FREE_OUTPUT_ERROR_INFO_ERR_NOT_ALLOCATED + uint8_t unused_1[6]; /* * This field is used in Output records to indicate that the output * is completely written to RAM. This field should be read as '1' @@ -53534,6 +57885,185 @@ struct pcie_ctx_hw_stats { uint64_t pcie_recovery_histogram; } __rte_packed; +/**************************** + * hwrm_stat_generic_qstats * + ****************************/ + + +/* hwrm_stat_generic_qstats_input (size:256b/32B) */ +struct hwrm_stat_generic_qstats_input { + /* The HWRM command request type. */ + uint16_t req_type; + /* + * The completion ring to send the completion event on. This should + * be the NQ ID returned from the `nq_alloc` HWRM command. + */ + uint16_t cmpl_ring; + /* + * The sequence ID is used by the driver for tracking multiple + * commands. This ID is treated as opaque data by the firmware and + * the value is returned in the `hwrm_resp_hdr` upon completion. + */ + uint16_t seq_id; + /* + * The target ID of the command: + * * 0x0-0xFFF8 - The function ID + * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors + * * 0xFFFD - Reserved for user-space HWRM interface + * * 0xFFFF - HWRM + */ + uint16_t target_id; + /* + * A physical address pointer pointing to a host buffer that the + * command's response data will be written. This can be either a host + * physical address (HPA) or a guest physical address (GPA) and must + * point to a physically contiguous block of memory. + */ + uint64_t resp_addr; + /* + * The size of the generic statistics buffer passed in the + * generic_stat_host_addr in bytes. + * Firmware will not exceed this size when it DMAs the + * statistics structure to the host. The actual DMA size + * will be returned in the response. + */ + uint16_t generic_stat_size; + uint8_t flags; + /* + * The bit should be set to 1 when request is for the counter mask + * representing the width of each of the stats counters, rather + * than counters themselves. + */ + #define HWRM_STAT_GENERIC_QSTATS_INPUT_FLAGS_COUNTER_MASK \ + UINT32_C(0x1) + uint8_t unused_0[5]; + /* + * This is the host address where + * generic statistics will be stored + */ + uint64_t generic_stat_host_addr; +} __rte_packed; + +/* hwrm_stat_generic_qstats_output (size:128b/16B) */ +struct hwrm_stat_generic_qstats_output { + /* The specific error status for the command. */ + uint16_t error_code; + /* The HWRM command request type. */ + uint16_t req_type; + /* The sequence ID from the original command. */ + uint16_t seq_id; + /* The length of the response data in number of bytes. */ + uint16_t resp_len; + /* The size of Generic Statistics block in bytes. */ + uint16_t generic_stat_size; + uint8_t unused_0[5]; + /* + * This field is used in Output records to indicate that the output + * is completely written to RAM. This field should be read as '1' + * to indicate that the output has been completely written. + * When writing a command completion or response to an internal + * processor, the order of writes has to be such that this field is + * written last. + */ + uint8_t valid; +} __rte_packed; + +/* Generic Statistic Format */ +/* generic_sw_hw_stats (size:1408b/176B) */ +struct generic_sw_hw_stats { + /* + * This is the number of TLP bytes that have been transmitted for + * the caller PF. + */ + uint64_t pcie_statistics_tx_tlp; + /* + * This is the number of TLP bytes that have been received + * for the caller PF. + */ + uint64_t pcie_statistics_rx_tlp; + /* Posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_posted; + /* Non-posted Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_nonposted; + /* Completion Header Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_hdr_cmpl; + /* Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_posted; + /* Non-Posted Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_nonposted; + /* Completion Data Flow Control credits available for the caller PF. */ + uint64_t pcie_credit_fc_data_cmpl; + /* + * Available Non-posted credit for target flow control reads or + * config for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_nonposted; + /* + * Available posted data credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_data_posted; + /* + * Available posted header credit for target flow control writes + * for the caller PF. + */ + uint64_t pcie_credit_fc_tgt_hdr_posted; + /* Available completion flow control header credits for the caller PF. */ + uint64_t pcie_credit_fc_cmpl_hdr_posted; + /* Available completion flow control data credits. */ + uint64_t pcie_credit_fc_cmpl_data_posted; + /* + * Displays Time information of the longest completon time from any of + * the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_longest; + /* + * Displays Time information of the shortest completon time from any of + * the 4 tags for the caller PF. The unit of time recorded is in + * microseconds. + */ + uint64_t pcie_cmpl_shortest; + /* + * This field contains the total number of CFCQ 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcq; + /* + * This field contains the total number of CFCS 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcs; + /* + * This field contains the total number of CFCC 'misses' observed for + * all the PF's. + */ + uint64_t cache_miss_count_cfcc; + /* + * This field contains the total number of CFCM 'misses' observed + * for all the PF's. + */ + uint64_t cache_miss_count_cfcm; + /* + * Total number of Doorbell messages dropped from the DB FIFO. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_dropped; + /* + * Total number of doorbell drops serviced. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_drops_serviced; + /* + * Total number of dropped doorbells recovered. + * This counter is only applicable for devices that support + * the hardware based doorbell drop recovery feature. + */ + uint64_t hw_db_recov_dbs_recovered; +} __rte_packed; + /********************** * hwrm_exec_fwd_resp * **********************/ @@ -55174,8 +59704,11 @@ struct hwrm_nvm_install_update_cmd_err { /* Firmware update failed due to Anti-rollback. */ #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK \ UINT32_C(0x3) + /* Firmware update does not support voltage regulators on the device. */ + #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT \ + UINT32_C(0x4) #define HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST \ - HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK + HWRM_NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT uint8_t unused_0[7]; } __rte_packed; -- 2.39.2 (Apple Git-143) --00000000000005431605ff331b65 Content-Type: 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