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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BN8NAM11FT028.mail.protection.outlook.com (10.13.176.225) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6500.49 via Frontend Transport; Fri, 30 Jun 2023 12:57:51 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Fri, 30 Jun 2023 05:57:47 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Fri, 30 Jun 2023 05:57:45 -0700 From: Bing Zhao To: , , , , CC: , , Subject: [PATCH] net/mlx5: reduce the counter pool name length Date: Fri, 30 Jun 2023 15:57:30 +0300 Message-ID: <20230630125730.435542-1-bingz@nvidia.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT028:EE_|IA0PR12MB7776:EE_ X-MS-Office365-Filtering-Correlation-Id: cebfffb1-5320-4e49-3be4-08db79699d09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2023 12:57:51.4337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cebfffb1-5320-4e49-3be4-08db79699d09 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7776 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org The name size of a rte_ring is RTE_MEMZONE_NAMESIZE with the value 32 by default. When creating a HWS counter pool cache, the final string format was "RG_MLX5_HWS_CNT_POOL_%u_cache/%u" and it could support less than 1000 variants. For example, if the first %u representing port id is 100 and it will take all the available characters then the second %u for queues will be discarded. If there was more than one rule creation queue, the rte_ring could not be created. By reducing the fixed character number and using hexadecimal format, the issue can be overcome with an assumption that not all the integer fields for queue index is used. Fixes: 13ea6bdcc7ee ("net/mlx5: support counters in cross port shared mode") Fixes: 4d368e1da3a4 ("net/mlx5: support flow counter action for HWS") Cc: jackmin@nvidia.com Cc: stable@dpdk.org Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_hws_cnt.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c index d98df68f39..18d80f34ba 100644 --- a/drivers/net/mlx5/mlx5_hws_cnt.c +++ b/drivers/net/mlx5/mlx5_hws_cnt.c @@ -419,8 +419,7 @@ mlx5_hws_cnt_pool_init(struct mlx5_dev_ctx_shared *sh, goto error; } for (qidx = 0; qidx < ccfg->q_num; qidx++) { - snprintf(mz_name, sizeof(mz_name), "%s_cache/%u", pcfg->name, - qidx); + snprintf(mz_name, sizeof(mz_name), "%s_qc/%x", pcfg->name, qidx); cntp->cache->qcache[qidx] = rte_ring_create(mz_name, ccfg->size, SOCKET_ID_ANY, RING_F_SP_ENQ | RING_F_SC_DEQ | @@ -612,12 +611,10 @@ mlx5_hws_cnt_pool_create(struct rte_eth_dev *dev, int ret = 0; size_t sz; - mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0, - SOCKET_ID_ANY); + mp_name = mlx5_malloc(MLX5_MEM_ZERO, RTE_MEMZONE_NAMESIZE, 0, SOCKET_ID_ANY); if (mp_name == NULL) goto error; - snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_POOL_%u", - dev->data->port_id); + snprintf(mp_name, RTE_MEMZONE_NAMESIZE, "MLX5_HWS_CNT_P_%x", dev->data->port_id); pcfg.name = mp_name; pcfg.request_num = pattr->nb_counters; pcfg.alloc_factor = HWS_CNT_ALLOC_FACTOR_DEFAULT; -- 2.34.1