From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id EE41742DD1; Tue, 4 Jul 2023 12:48:42 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id EE0F142D2C; Tue, 4 Jul 2023 12:48:40 +0200 (CEST) Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by mails.dpdk.org (Postfix) with ESMTP id 6DD5242BC9 for ; Tue, 4 Jul 2023 12:48:39 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z2F4RcwDhbVqpNK2jZWy/99dtsdgPrfkcdyaVt3PB7MYoBWO7pYDjIZyLPVV3FZ+0cNvZWthPBWyv2lbOt8N2HWOL7gXhayTkuz6fbtPggBJ4p4BVFBAle5pak0Lzvx/YRLiaITPO4yJlQuTpnNErh58W69qbmZIcpUqq7Ha8lALJ0I1CqtQF4nh20zuUp6uDd/Cq0Wn31sajOSN0LqoLklNr130io1nCfBUluAeeX+Ur6DyDHg/kfumLFf8AzzAh6crkrZq7+5lBYwXpxoTFnKWk9at58rFWarKWBZ23kyP/U4d21xyCYEry6C1isH0ZCKkgWluKqxCMSGmhmVgMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=+VoFDzi8ASKM6OvldCv5dyKY3OEw7zHyhhYx6lchfJ0=; b=Rvgw8duX42indk7EQFlGGKt2i5hMrQkiwAoO6E/mXXTX97u3Ydm18ZiWP5NDDnNH++ivJ/AsMRfHQ4DPTNAgk6u9OwO0QG4GlfT+i0KblJOCTTL9jwCKyJfAYMC0G9iS6DjkBspptA21DRX7igzCHph9PY4F1SgySzCCz6VqQRpWn0OBFvXMMF5rcpz+L2Qk+jnBBwiQ+UUDOPyCdKGrZzvdYytdicySqtiwQBmanixfXWIy6faCWzcobuAvFemhyzHErJe9jqO+9iYu824t4ZvqCRjYAlyJVKRotxZUyii/HSw267Y8qAaaqFdE/ou/4W+Z7/xqYyTKpL1sXkl40g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=+VoFDzi8ASKM6OvldCv5dyKY3OEw7zHyhhYx6lchfJ0=; b=m47gJGQke/EvhARrNVGC09Y8V+FMAOZMoaXgE0rzI2GZxTtiM0VjwMhgG5MJburxw2+YuVqZqhxm1Hg54D1svSEdwCMPhj2vwmF9ksjz7MDOiJzXKG2biIktMTVQU+UfU1qIGton4o2VApmbw+p9SJnjYZjBvFabIR54SfePaIQ+bPBE/gLxT8QUbKhr2d9L0caZC+rBFWs+o9ZI4pV3ORVQzgOr+kHFhiKcvFLTxNCC+8QhyGSzgCf2gV2L10V2cZ3gXZrGNU079F95MGCDCdZ2BfF9vAQiEI5mI1ynPDxXGvFXniq4qG5Xdddaiqx7m2ZOIsUk9EpE3KzikjJj1w== Received: from DM6PR03CA0062.namprd03.prod.outlook.com (2603:10b6:5:100::39) by PH8PR12MB6987.namprd12.prod.outlook.com (2603:10b6:510:1be::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6544.24; Tue, 4 Jul 2023 10:48:37 +0000 Received: from DM6NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:5:100:cafe::9c) by DM6PR03CA0062.outlook.office365.com (2603:10b6:5:100::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6565.18 via Frontend Transport; Tue, 4 Jul 2023 10:48:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DM6NAM11FT049.mail.protection.outlook.com (10.13.172.188) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.43 via Frontend Transport; Tue, 4 Jul 2023 10:48:37 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.5; Tue, 4 Jul 2023 03:48:29 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 4 Jul 2023 03:48:28 -0700 Received: from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37 via Frontend Transport; Tue, 4 Jul 2023 03:48:26 -0700 From: Itamar Gozlan To: , , , , , Ori Kam CC: Subject: [v1 5/5] net/mlx5/hws: support default miss action on FDB Date: Tue, 4 Jul 2023 13:46:45 +0300 Message-ID: <20230704104645.19800-5-igozlan@nvidia.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20230704104645.19800-1-igozlan@nvidia.com> References: <20230702045758.23244-4-igozlan@nvidia.com> <20230704104645.19800-1-igozlan@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT049:EE_|PH8PR12MB6987:EE_ X-MS-Office365-Filtering-Correlation-Id: c21e3ea9-f0ec-4bfb-4068-08db7c7c38e9 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HUSnYknsyCUqcwXudGJODqdUd6MTlxN7sMBP889W2lLEFNZMxCpJUUKLZxL7GqMYjYIRjD34pN0sCn7a3lXMOazJMPZzHUSA/QeRaKrbkJ9alBx249JevBKy5h6bNTfwvwRCl12f5zSM3hXiE5Onf6Wg50uhj3GA5zfDGdAWFcJf2GnHrnZYlgxlujHN1D7HRnKsFjX+wfKu/RJum+qAW5lTDl6ahxc5UCQI2nyQcNWimk0bq6gKvPRTxXOYFjGCPVMP0CBf8NdfoYS80kJDyv18vH9tZb7N9qGxUk1BOi/TFmzCxYoR/XhWycXoTtY3+dVGs1NSlRdgNHpe6k4XIPCG16yX0M4yPO06x8dX8Pmf0ZDHYmNXTsaNr6fxr9Qk0ISpjV5LyDYlXQ5RJqQ/DeljndbkGyjom3gCgUFsUDLI2eq0VGPtSJh/r4ezMtl4Q3kGlhLmJzGm88Vn48+DUAQE0agq14o1WYJP1P1H09e/1d/IgD6o8JrYyxlG/3hhvWR9IGj5malSSvdNXZBt2pz5PlMEXH3jh/zCM5gRKbHDSuZXqSE6hzqY/gHY1wQ4ZzGfB8hX4n1MiZk5Ar+w1Dgjw99VSUjZfmj0uyJZ4hXj7GcNcdeAQGCKzGJcw17mo9OyFmfSXHK0conW95hUpoGCYyTFbiMEMCOl7NYmrc2uJyqmmmkxu2yz1piv92rBpwJsN2MERuVb4geTwBgOaM5cNNl3T94lSFq1UD6LjHJ4OApC5qym/JY+xIfV9YFC X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230028)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199021)(40470700004)(46966006)(36840700001)(26005)(478600001)(1076003)(82740400003)(6666004)(86362001)(6286002)(2616005)(186003)(36860700001)(6636002)(4326008)(70586007)(356005)(336012)(7636003)(110136005)(83380400001)(426003)(7696005)(70206006)(316002)(47076005)(8676002)(8936002)(40460700003)(41300700001)(2906002)(40480700001)(55016003)(5660300002)(82310400005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jul 2023 10:48:37.4250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c21e3ea9-f0ec-4bfb-4068-08db7c7c38e9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6987 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Add the support for default miss on HWS FDB, this implementation was missing until now. Default miss can be used for more efficient miss flow instead of going to an empty matcher or some defecated empty table. Signed-off-by: Alex Vesker Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_action.c | 27 ++++++++++++++++++++------- drivers/net/mlx5/hws/mlx5dr_table.c | 6 +----- 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index 74f4e60863..920099ba5b 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -322,10 +322,12 @@ int mlx5dr_action_root_build_attr(struct mlx5dr_rule_action rule_actions[], return 0; } -static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_attr, - struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr, - enum mlx5dr_table_type table_type, - bool is_mirror) +static bool +mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, + struct mlx5dr_cmd_stc_modify_attr *stc_attr, + struct mlx5dr_cmd_stc_modify_attr *fixup_stc_attr, + enum mlx5dr_table_type table_type, + bool is_mirror) { struct mlx5dr_devx_obj *devx_obj; bool use_fixup = false; @@ -348,6 +350,17 @@ static bool mlx5dr_action_fixup_stc_attr(struct mlx5dr_cmd_stc_modify_attr *stc_ use_fixup = true; break; + case MLX5_IFC_STC_ACTION_TYPE_ALLOW: + if (fw_tbl_type == FS_FT_FDB_TX || fw_tbl_type == FS_FT_FDB_RX) { + fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT; + fixup_stc_attr->action_offset = stc_attr->action_offset; + fixup_stc_attr->stc_offset = stc_attr->stc_offset; + fixup_stc_attr->vport.esw_owner_vhca_id = ctx->caps->vhca_id; + fixup_stc_attr->vport.vport_num = ctx->caps->eswitch_manager_vport_number; + use_fixup = true; + } + break; + case MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_VPORT: if (stc_attr->vport.vport_num != WIRE_PORT) break; @@ -397,7 +410,7 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx, devx_obj_0 = mlx5dr_pool_chunk_get_base_devx_obj(stc_pool, stc); /* According to table/action limitation change the stc_attr */ - use_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, table_type, false); + use_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, &fixup_stc_attr, table_type, false); ret = mlx5dr_cmd_stc_modify(devx_obj_0, use_fixup ? &fixup_stc_attr : stc_attr); if (ret) { DR_LOG(ERR, "Failed to modify STC action_type %d tbl_type %d", @@ -411,7 +424,8 @@ int mlx5dr_action_alloc_single_stc(struct mlx5dr_context *ctx, devx_obj_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(stc_pool, stc); - use_fixup = mlx5dr_action_fixup_stc_attr(stc_attr, &fixup_stc_attr, + use_fixup = mlx5dr_action_fixup_stc_attr(ctx, stc_attr, + &fixup_stc_attr, table_type, true); ret = mlx5dr_cmd_stc_modify(devx_obj_1, use_fixup ? &fixup_stc_attr : stc_attr); if (ret) { @@ -491,7 +505,6 @@ static void mlx5dr_action_fill_stc_attr(struct mlx5dr_action *action, case MLX5DR_ACTION_TYP_MISS: attr->action_type = MLX5_IFC_STC_ACTION_TYPE_ALLOW; attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; - /* TODO Need to support default miss for FDB */ break; case MLX5DR_ACTION_TYP_CTR: attr->id = obj->id; diff --git a/drivers/net/mlx5/hws/mlx5dr_table.c b/drivers/net/mlx5/hws/mlx5dr_table.c index c18ee7c552..f91f04d924 100644 --- a/drivers/net/mlx5/hws/mlx5dr_table.c +++ b/drivers/net/mlx5/hws/mlx5dr_table.c @@ -24,7 +24,6 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl) struct mlx5dr_cmd_forward_tbl *default_miss; struct mlx5dr_context *ctx = tbl->ctx; uint8_t tbl_type = tbl->type; - uint32_t vport; if (tbl->type != MLX5DR_TABLE_TYPE_FDB) return 0; @@ -38,12 +37,9 @@ mlx5dr_table_up_default_fdb_miss_tbl(struct mlx5dr_table *tbl) ft_attr.level = tbl->ctx->caps->fdb_ft.max_level; /* The last level */ ft_attr.rtc_valid = false; - assert(ctx->caps->eswitch_manager); - vport = ctx->caps->eswitch_manager_vport_number; - fte_attr.action_flags = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; fte_attr.destination_type = MLX5_FLOW_DESTINATION_TYPE_VPORT; - fte_attr.destination_id = vport; + fte_attr.destination_id = ctx->caps->eswitch_manager_vport_number; default_miss = mlx5dr_cmd_forward_tbl_create(mlx5dr_context_get_local_ibv(ctx), &ft_attr, &fte_attr); -- 2.18.1