From: beilei.xing@intel.com
To: jingjing.wu@intel.com, mingxia.liu@intel.com
Cc: dev@dpdk.org, Beilei Xing <beilei.xing@intel.com>,
Qi Zhang <qi.z.zhang@intel.com>
Subject: [PATCH 01/19] net/cpfl: refine devargs parse and process
Date: Wed, 9 Aug 2023 15:51:16 +0000 [thread overview]
Message-ID: <20230809155134.539287-2-beilei.xing@intel.com> (raw)
In-Reply-To: <20230809155134.539287-1-beilei.xing@intel.com>
From: Beilei Xing <beilei.xing@intel.com>
1. Keep devargs in adapter.
2. Refine handling the case with no vport be specified in devargs.
3. Separate devargs parse and devargs process
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
---
drivers/net/cpfl/cpfl_ethdev.c | 154 ++++++++++++++++++---------------
drivers/net/cpfl/cpfl_ethdev.h | 1 +
2 files changed, 84 insertions(+), 71 deletions(-)
diff --git a/drivers/net/cpfl/cpfl_ethdev.c b/drivers/net/cpfl/cpfl_ethdev.c
index c4ca9343c3..46b3a52e49 100644
--- a/drivers/net/cpfl/cpfl_ethdev.c
+++ b/drivers/net/cpfl/cpfl_ethdev.c
@@ -1407,12 +1407,12 @@ parse_bool(const char *key, const char *value, void *args)
}
static int
-cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter,
- struct cpfl_devargs *cpfl_args)
+cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)
{
struct rte_devargs *devargs = pci_dev->device.devargs;
+ struct cpfl_devargs *cpfl_args = &adapter->devargs;
struct rte_kvargs *kvlist;
- int i, ret;
+ int ret;
cpfl_args->req_vport_nb = 0;
@@ -1445,31 +1445,6 @@ cpfl_parse_devargs(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adap
if (ret != 0)
goto fail;
- /* check parsed devargs */
- if (adapter->cur_vport_nb + cpfl_args->req_vport_nb >
- adapter->max_vport_nb) {
- PMD_INIT_LOG(ERR, "Total vport number can't be > %d",
- adapter->max_vport_nb);
- ret = -EINVAL;
- goto fail;
- }
-
- for (i = 0; i < cpfl_args->req_vport_nb; i++) {
- if (cpfl_args->req_vports[i] > adapter->max_vport_nb - 1) {
- PMD_INIT_LOG(ERR, "Invalid vport id %d, it should be 0 ~ %d",
- cpfl_args->req_vports[i], adapter->max_vport_nb - 1);
- ret = -EINVAL;
- goto fail;
- }
-
- if (adapter->cur_vports & RTE_BIT32(cpfl_args->req_vports[i])) {
- PMD_INIT_LOG(ERR, "Vport %d has been requested",
- cpfl_args->req_vports[i]);
- ret = -EINVAL;
- goto fail;
- }
- }
-
fail:
rte_kvargs_free(kvlist);
return ret;
@@ -1915,15 +1890,79 @@ cpfl_adapter_ext_deinit(struct cpfl_adapter_ext *adapter)
adapter->vports = NULL;
}
+static int
+cpfl_vport_devargs_process(struct cpfl_adapter_ext *adapter)
+{
+ struct cpfl_devargs *devargs = &adapter->devargs;
+ int i;
+
+ /* refine vport number, at least 1 vport */
+ if (devargs->req_vport_nb == 0) {
+ devargs->req_vport_nb = 1;
+ devargs->req_vports[0] = 0;
+ }
+
+ /* check parsed devargs */
+ if (adapter->cur_vport_nb + devargs->req_vport_nb >
+ adapter->max_vport_nb) {
+ PMD_INIT_LOG(ERR, "Total vport number can't be > %d",
+ adapter->max_vport_nb);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < devargs->req_vport_nb; i++) {
+ if (devargs->req_vports[i] > adapter->max_vport_nb - 1) {
+ PMD_INIT_LOG(ERR, "Invalid vport id %d, it should be 0 ~ %d",
+ devargs->req_vports[i], adapter->max_vport_nb - 1);
+ return -EINVAL;
+ }
+
+ if (adapter->cur_vports & RTE_BIT32(devargs->req_vports[i])) {
+ PMD_INIT_LOG(ERR, "Vport %d has been requested",
+ devargs->req_vports[i]);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+static int
+cpfl_vport_create(struct rte_pci_device *pci_dev, struct cpfl_adapter_ext *adapter)
+{
+ struct cpfl_vport_param vport_param;
+ char name[RTE_ETH_NAME_MAX_LEN];
+ int ret, i;
+
+ for (i = 0; i < adapter->devargs.req_vport_nb; i++) {
+ vport_param.adapter = adapter;
+ vport_param.devarg_id = adapter->devargs.req_vports[i];
+ vport_param.idx = cpfl_vport_idx_alloc(adapter);
+ if (vport_param.idx == CPFL_INVALID_VPORT_IDX) {
+ PMD_INIT_LOG(ERR, "No space for vport %u", vport_param.devarg_id);
+ break;
+ }
+ snprintf(name, sizeof(name), "net_%s_vport_%d",
+ pci_dev->device.name,
+ adapter->devargs.req_vports[i]);
+ ret = rte_eth_dev_create(&pci_dev->device, name,
+ sizeof(struct cpfl_vport),
+ NULL, NULL, cpfl_dev_vport_init,
+ &vport_param);
+ if (ret != 0)
+ PMD_DRV_LOG(ERR, "Failed to create vport %d",
+ vport_param.devarg_id);
+ }
+
+ return 0;
+}
+
static int
cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
{
- struct cpfl_vport_param vport_param;
struct cpfl_adapter_ext *adapter;
- struct cpfl_devargs devargs;
- char name[RTE_ETH_NAME_MAX_LEN];
- int i, retval;
+ int retval;
if (!cpfl_adapter_list_init) {
rte_spinlock_init(&cpfl_adapter_lock);
@@ -1938,6 +1977,12 @@ cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
return -ENOMEM;
}
+ retval = cpfl_parse_devargs(pci_dev, adapter);
+ if (retval != 0) {
+ PMD_INIT_LOG(ERR, "Failed to parse private devargs");
+ return retval;
+ }
+
retval = cpfl_adapter_ext_init(pci_dev, adapter);
if (retval != 0) {
PMD_INIT_LOG(ERR, "Failed to init adapter.");
@@ -1948,49 +1993,16 @@ cpfl_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
TAILQ_INSERT_TAIL(&cpfl_adapter_list, adapter, next);
rte_spinlock_unlock(&cpfl_adapter_lock);
- retval = cpfl_parse_devargs(pci_dev, adapter, &devargs);
+ retval = cpfl_vport_devargs_process(adapter);
if (retval != 0) {
- PMD_INIT_LOG(ERR, "Failed to parse private devargs");
+ PMD_INIT_LOG(ERR, "Failed to process vport devargs");
goto err;
}
- if (devargs.req_vport_nb == 0) {
- /* If no vport devarg, create vport 0 by default. */
- vport_param.adapter = adapter;
- vport_param.devarg_id = 0;
- vport_param.idx = cpfl_vport_idx_alloc(adapter);
- if (vport_param.idx == CPFL_INVALID_VPORT_IDX) {
- PMD_INIT_LOG(ERR, "No space for vport %u", vport_param.devarg_id);
- return 0;
- }
- snprintf(name, sizeof(name), "cpfl_%s_vport_0",
- pci_dev->device.name);
- retval = rte_eth_dev_create(&pci_dev->device, name,
- sizeof(struct cpfl_vport),
- NULL, NULL, cpfl_dev_vport_init,
- &vport_param);
- if (retval != 0)
- PMD_DRV_LOG(ERR, "Failed to create default vport 0");
- } else {
- for (i = 0; i < devargs.req_vport_nb; i++) {
- vport_param.adapter = adapter;
- vport_param.devarg_id = devargs.req_vports[i];
- vport_param.idx = cpfl_vport_idx_alloc(adapter);
- if (vport_param.idx == CPFL_INVALID_VPORT_IDX) {
- PMD_INIT_LOG(ERR, "No space for vport %u", vport_param.devarg_id);
- break;
- }
- snprintf(name, sizeof(name), "cpfl_%s_vport_%d",
- pci_dev->device.name,
- devargs.req_vports[i]);
- retval = rte_eth_dev_create(&pci_dev->device, name,
- sizeof(struct cpfl_vport),
- NULL, NULL, cpfl_dev_vport_init,
- &vport_param);
- if (retval != 0)
- PMD_DRV_LOG(ERR, "Failed to create vport %d",
- vport_param.devarg_id);
- }
+ retval = cpfl_vport_create(pci_dev, adapter);
+ if (retval != 0) {
+ PMD_INIT_LOG(ERR, "Failed to create vports.");
+ goto err;
}
return 0;
diff --git a/drivers/net/cpfl/cpfl_ethdev.h b/drivers/net/cpfl/cpfl_ethdev.h
index 2e42354f70..b637bf2e45 100644
--- a/drivers/net/cpfl/cpfl_ethdev.h
+++ b/drivers/net/cpfl/cpfl_ethdev.h
@@ -115,6 +115,7 @@ struct cpfl_adapter_ext {
uint16_t cur_vport_nb;
uint16_t used_vecs_num;
+ struct cpfl_devargs devargs;
};
TAILQ_HEAD(cpfl_adapter_list, cpfl_adapter_ext);
--
2.34.1
next prev parent reply other threads:[~2023-08-09 7:33 UTC|newest]
Thread overview: 89+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-09 15:51 [PATCH 00/19] net/cpfl: support port representor beilei.xing
2023-08-09 15:51 ` beilei.xing [this message]
2023-08-09 15:51 ` [PATCH 02/19] net/cpfl: introduce interface structure beilei.xing
2023-08-09 15:51 ` [PATCH 03/19] net/cpfl: add cp channel beilei.xing
2023-08-09 15:51 ` [PATCH 04/19] net/cpfl: enable vport mapping beilei.xing
2023-08-09 15:51 ` [PATCH 05/19] net/cpfl: parse representor devargs beilei.xing
2023-08-09 15:51 ` [PATCH 06/19] net/cpfl: support probe again beilei.xing
2023-08-09 15:51 ` [PATCH 07/19] net/cpfl: create port representor beilei.xing
2023-08-09 15:51 ` [PATCH 08/19] net/cpfl: support vport list/info get beilei.xing
2023-08-09 15:51 ` [PATCH 09/19] net/cpfl: update vport info before creating representor beilei.xing
2023-08-09 15:51 ` [PATCH 10/19] net/cpfl: refine handle virtual channel message beilei.xing
2023-08-09 15:51 ` [PATCH 11/19] net/cpfl: add exceptional vport beilei.xing
2023-08-09 15:51 ` [PATCH 12/19] net/cpfl: support representor Rx/Tx queue setup beilei.xing
2023-08-09 15:51 ` [PATCH 13/19] net/cpfl: support link update for representor beilei.xing
2023-08-09 15:51 ` [PATCH 14/19] net/cpfl: add stats ops " beilei.xing
2023-08-09 15:51 ` [PATCH 15/19] common/idpf: refine inline function beilei.xing
2023-08-09 15:51 ` [PATCH 16/19] net/cpfl: support representor data path beilei.xing
2023-08-09 15:51 ` [PATCH 17/19] net/cpfl: support dispatch process beilei.xing
2023-08-09 15:51 ` [PATCH 18/19] net/cpfl: add dispatch service beilei.xing
2023-08-09 15:51 ` [PATCH 19/19] doc: update release notes for representor beilei.xing
2023-08-16 15:05 ` [PATCH v2 00/12] net/cpfl: support port representor beilei.xing
2023-08-16 15:05 ` [PATCH v2 01/12] net/cpfl: refine devargs parse and process beilei.xing
2023-08-16 15:05 ` [PATCH v2 02/12] net/cpfl: introduce interface structure beilei.xing
2023-08-16 15:05 ` [PATCH v2 03/12] net/cpfl: add cp channel beilei.xing
2023-08-16 15:05 ` [PATCH v2 04/12] net/cpfl: enable vport mapping beilei.xing
2023-08-16 15:05 ` [PATCH v2 05/12] net/cpfl: parse representor devargs beilei.xing
2023-08-16 15:05 ` [PATCH v2 06/12] net/cpfl: support probe again beilei.xing
2023-08-16 15:05 ` [PATCH v2 07/12] net/cpfl: create port representor beilei.xing
2023-09-05 7:35 ` Liu, Mingxia
2023-09-05 8:30 ` Liu, Mingxia
2023-08-16 15:05 ` [PATCH v2 08/12] net/cpfl: support vport list/info get beilei.xing
2023-08-16 15:05 ` [PATCH v2 09/12] net/cpfl: update vport info before creating representor beilei.xing
2023-09-06 2:33 ` Liu, Mingxia
2023-08-16 15:05 ` [PATCH v2 10/12] net/cpfl: refine handle virtual channel message beilei.xing
2023-08-16 15:05 ` [PATCH v2 11/12] net/cpfl: support link update for representor beilei.xing
2023-08-16 15:05 ` [PATCH v2 12/12] net/cpfl: support Rx/Tx queue setup " beilei.xing
2023-09-06 3:02 ` Liu, Mingxia
2023-09-07 15:15 ` [PATCH v3 00/11] net/cpfl: support port representor beilei.xing
2023-09-07 15:15 ` [PATCH v3 01/11] net/cpfl: refine devargs parse and process beilei.xing
2023-09-07 15:15 ` [PATCH v3 02/11] net/cpfl: introduce interface structure beilei.xing
2023-09-07 15:15 ` [PATCH v3 03/11] net/cpfl: refine handle virtual channel message beilei.xing
2023-09-07 15:15 ` [PATCH v3 04/11] net/cpfl: introduce CP channel API beilei.xing
2023-09-07 15:16 ` [PATCH v3 05/11] net/cpfl: enable vport mapping beilei.xing
2023-09-07 15:16 ` [PATCH v3 06/11] net/cpfl: parse representor devargs beilei.xing
2023-09-07 15:16 ` [PATCH v3 07/11] net/cpfl: support probe again beilei.xing
2023-09-07 15:16 ` [PATCH v3 08/11] net/cpfl: create port representor beilei.xing
2023-09-07 15:16 ` [PATCH v3 09/11] net/cpfl: support vport list/info get beilei.xing
2023-09-07 15:16 ` [PATCH v3 10/11] net/cpfl: update vport info before creating representor beilei.xing
2023-09-07 15:16 ` [PATCH v3 11/11] net/cpfl: support link update for representor beilei.xing
2023-09-08 11:16 ` [PATCH v4 00/10] net/cpfl: support port representor beilei.xing
2023-09-08 11:16 ` [PATCH v4 01/10] net/cpfl: refine devargs parse and process beilei.xing
2023-09-08 11:16 ` [PATCH v4 02/10] net/cpfl: introduce interface structure beilei.xing
2023-09-09 2:08 ` Wu, Jingjing
2023-09-08 11:16 ` [PATCH v4 03/10] net/cpfl: refine handle virtual channel message beilei.xing
2023-09-09 2:13 ` Wu, Jingjing
2023-09-08 11:16 ` [PATCH v4 04/10] net/cpfl: introduce CP channel API beilei.xing
2023-09-08 11:16 ` [PATCH v4 05/10] net/cpfl: enable vport mapping beilei.xing
2023-09-08 11:16 ` [PATCH v4 06/10] net/cpfl: parse representor devargs beilei.xing
2023-09-08 11:16 ` [PATCH v4 07/10] net/cpfl: support probe again beilei.xing
2023-09-08 11:16 ` [PATCH v4 08/10] net/cpfl: support vport list/info get beilei.xing
2023-09-09 2:34 ` Wu, Jingjing
2023-09-08 11:17 ` [PATCH v4 09/10] net/cpfl: create port representor beilei.xing
2023-09-09 3:04 ` Wu, Jingjing
2023-09-08 11:17 ` [PATCH v4 10/10] net/cpfl: support link update for representor beilei.xing
2023-09-09 3:05 ` Wu, Jingjing
2023-09-12 16:26 ` [PATCH v5 00/10] net/cpfl: support port representor beilei.xing
2023-09-12 16:26 ` [PATCH v5 01/10] net/cpfl: refine devargs parse and process beilei.xing
2023-09-12 16:26 ` [PATCH v5 02/10] net/cpfl: introduce interface structure beilei.xing
2023-09-12 16:26 ` [PATCH v5 03/10] net/cpfl: refine handle virtual channel message beilei.xing
2023-09-12 16:26 ` [PATCH v5 04/10] net/cpfl: introduce CP channel API beilei.xing
2023-09-12 16:26 ` [PATCH v5 05/10] net/cpfl: enable vport mapping beilei.xing
2023-09-12 16:26 ` [PATCH v5 06/10] net/cpfl: support vport list/info get beilei.xing
2023-09-12 16:26 ` [PATCH v5 07/10] net/cpfl: parse representor devargs beilei.xing
2023-09-12 16:26 ` [PATCH v5 08/10] net/cpfl: support probe again beilei.xing
2023-09-12 16:26 ` [PATCH v5 09/10] net/cpfl: create port representor beilei.xing
2023-09-12 16:26 ` [PATCH v5 10/10] net/cpfl: support link update for representor beilei.xing
2023-09-12 17:30 ` [PATCH v6 00/10] net/cpfl: support port representor beilei.xing
2023-09-12 17:30 ` [PATCH v6 01/10] net/cpfl: refine devargs parse and process beilei.xing
2023-09-12 17:30 ` [PATCH v6 02/10] net/cpfl: introduce interface structure beilei.xing
2023-09-12 17:30 ` [PATCH v6 03/10] net/cpfl: refine handle virtual channel message beilei.xing
2023-09-12 17:30 ` [PATCH v6 04/10] net/cpfl: introduce CP channel API beilei.xing
2023-09-12 17:30 ` [PATCH v6 05/10] net/cpfl: enable vport mapping beilei.xing
2023-09-12 17:30 ` [PATCH v6 06/10] net/cpfl: support vport list/info get beilei.xing
2023-09-12 17:30 ` [PATCH v6 07/10] net/cpfl: parse representor devargs beilei.xing
2023-09-12 17:30 ` [PATCH v6 08/10] net/cpfl: support probe again beilei.xing
2023-09-12 17:30 ` [PATCH v6 09/10] net/cpfl: create port representor beilei.xing
2023-09-12 17:30 ` [PATCH v6 10/10] net/cpfl: support link update for representor beilei.xing
2023-09-13 1:01 ` [PATCH v6 00/10] net/cpfl: support port representor Wu, Jingjing
2023-09-13 5:41 ` Zhang, Qi Z
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