From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>,
Sunil Kumar Kori <skori@marvell.com>,
Satha Rao <skoteshwar@marvell.com>
Cc: <jerinj@marvell.com>, <dev@dpdk.org>,
Rakesh Kudurumalla <rkudurumalla@marvell.com>
Subject: [PATCH 02/31] common/cnxk: optimize time while configuring fc on VF
Date: Fri, 11 Aug 2023 14:27:36 +0530 [thread overview]
Message-ID: <20230811085805.441256-2-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20230811085805.441256-1-ndabilpuram@marvell.com>
From: Rakesh Kudurumalla <rkudurumalla@marvell.com>
PFC configuration function is taking 8 ms due
to mailbox communication to check whether sso is
connected to RQ and whether back pressure is enabled
on each aura. To optimize this time we are updating
aura attributes in nixlf and sso_ena parameter
in RQ during write configuration and the same updated
value is accessed while configuring flow control,
reducing time to 6 ms.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
---
drivers/common/cnxk/roc_nix_fc.c | 47 ++++++++----------------------
drivers/common/cnxk/roc_npa.c | 16 +++++++++-
drivers/common/cnxk/roc_npa_priv.h | 6 ++++
3 files changed, 33 insertions(+), 36 deletions(-)
diff --git a/drivers/common/cnxk/roc_nix_fc.c b/drivers/common/cnxk/roc_nix_fc.c
index 1f5ef960da..d58b35268e 100644
--- a/drivers/common/cnxk/roc_nix_fc.c
+++ b/drivers/common/cnxk/roc_nix_fc.c
@@ -285,15 +285,11 @@ nix_fc_rq_config_set(struct roc_nix *roc_nix, struct roc_nix_fc_cfg *fc_cfg)
struct roc_nix_fc_cfg tmp;
uint64_t pool_drop_pct;
struct roc_nix_rq *rq;
- int sso_ena = 0, rc;
+ int rc;
rq = nix->rqs[fc_cfg->rq_cfg.rq];
- /* Check whether RQ is connected to SSO or not */
- sso_ena = roc_nix_rq_is_sso_enable(roc_nix, fc_cfg->rq_cfg.rq);
- if (sso_ena < 0)
- return -EINVAL;
- if (sso_ena) {
+ if (rq->sso_ena) {
pool_drop_pct = fc_cfg->rq_cfg.pool_drop_pct;
/* Use default value for zero pct */
if (fc_cfg->rq_cfg.enable && !pool_drop_pct)
@@ -486,12 +482,10 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
uint32_t aura_id = roc_npa_aura_handle_to_aura(pool_id);
struct nix *nix = roc_nix_to_nix_priv(roc_nix);
struct npa_lf *lf = idev_npa_obj_get();
- struct npa_aq_enq_req *req;
- struct npa_aq_enq_rsp *rsp;
+ struct npa_aura_attr *aura_attr;
uint8_t bp_thresh, bp_intf;
- struct mbox *mbox;
uint16_t bpid;
- int rc, i;
+ int i;
if (roc_nix_is_sdp(roc_nix))
return;
@@ -499,30 +493,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
if (!lf)
return;
- mbox = lf->mbox;
- req = mbox_alloc_msg_npa_aq_enq(mbox_get(mbox));
- if (req == NULL) {
- mbox_put(mbox);
- return;
- }
-
- req->aura_id = aura_id;
- req->ctype = NPA_AQ_CTYPE_AURA;
- req->op = NPA_AQ_INSTOP_READ;
-
- rc = mbox_process_msg(mbox, (void *)&rsp);
- mbox_put(mbox);
- if (rc) {
- plt_nix_dbg("Failed to read context of aura 0x%" PRIx64, pool_id);
- return;
- }
+ aura_attr = &lf->aura_attr[aura_id];
bp_intf = 1 << nix->is_nix1;
- bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, rsp->aura.limit >> rsp->aura.shift);
+ bp_thresh = NIX_RQ_AURA_THRESH(drop_percent, aura_attr->limit >> aura_attr->shift);
- bpid = (rsp->aura.bp_ena & 0x1) ? rsp->aura.nix0_bpid : rsp->aura.nix1_bpid;
+ bpid = (aura_attr->bp_ena & 0x1) ? aura_attr->nix0_bpid : aura_attr->nix1_bpid;
/* BP is already enabled. */
- if (rsp->aura.bp_ena && ena) {
+ if (aura_attr->bp_ena && ena) {
/* Disable BP if BPIDs don't match and couldn't add new BPID. */
if (bpid != nix->bpid[tc]) {
uint16_t bpid_new = NIX_BPID_INVALID;
@@ -537,7 +515,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
plt_err("Enabling backpressue failed on aura 0x%" PRIx64,
pool_id);
} else {
- lf->aura_attr[aura_id].ref_count++;
+ aura_attr->ref_count++;
plt_info("Ignoring port=%u tc=%u config on shared aura 0x%" PRIx64,
roc_nix->port_id, tc, pool_id);
}
@@ -547,14 +525,14 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
}
/* BP was previously enabled but now disabled skip. */
- if (rsp->aura.bp && ena)
+ if (aura_attr->bp && ena)
return;
if (ena) {
if (roc_npa_aura_bp_configure(pool_id, nix->bpid[tc], bp_intf, bp_thresh, true))
plt_err("Enabling backpressue failed on aura 0x%" PRIx64, pool_id);
else
- lf->aura_attr[aura_id].ref_count++;
+ aura_attr->ref_count++;
} else {
bool found = !!force;
@@ -564,8 +542,7 @@ roc_nix_fc_npa_bp_cfg(struct roc_nix *roc_nix, uint64_t pool_id, uint8_t ena, ui
found = true;
if (!found)
return;
- else if ((lf->aura_attr[aura_id].ref_count > 0) &&
- --lf->aura_attr[aura_id].ref_count)
+ else if ((aura_attr->ref_count > 0) && --(aura_attr->ref_count))
return;
if (roc_npa_aura_bp_configure(pool_id, 0, 0, 0, false))
diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index 3b9a70028b..d5c3a53b9b 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -535,6 +535,8 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
if (rc)
goto stack_mem_free;
+ lf->aura_attr[aura_id].shift = aura->shift;
+ lf->aura_attr[aura_id].limit = aura->limit;
*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);
/* Update aura count */
roc_npa_aura_op_cnt_set(*aura_handle, 0, block_count);
@@ -657,6 +659,8 @@ npa_aura_alloc(struct npa_lf *lf, const uint32_t block_count, int pool_id,
if (rc)
return rc;
+ lf->aura_attr[aura_id].shift = aura->shift;
+ lf->aura_attr[aura_id].limit = aura->limit;
*aura_handle = roc_npa_aura_handle_gen(aura_id, lf->base);
return 0;
@@ -735,6 +739,9 @@ roc_npa_aura_limit_modify(uint64_t aura_handle, uint16_t aura_limit)
aura_req->aura.limit = aura_limit;
aura_req->aura_mask.limit = ~(aura_req->aura_mask.limit);
rc = mbox_process(mbox);
+ if (rc)
+ goto exit;
+ lf->aura_attr[aura_req->aura_id].limit = aura_req->aura.limit;
exit:
mbox_put(mbox);
return rc;
@@ -931,7 +938,14 @@ roc_npa_aura_bp_configure(uint64_t aura_handle, uint16_t bpid, uint8_t bp_intf,
req->aura.bp_ena = bp_intf;
req->aura_mask.bp_ena = ~(req->aura_mask.bp_ena);
- mbox_process(mbox);
+ rc = mbox_process(mbox);
+ if (rc)
+ goto fail;
+
+ lf->aura_attr[aura_id].nix0_bpid = req->aura.nix0_bpid;
+ lf->aura_attr[aura_id].nix1_bpid = req->aura.nix1_bpid;
+ lf->aura_attr[aura_id].bp_ena = req->aura.bp_ena;
+ lf->aura_attr[aura_id].bp = req->aura.bp;
fail:
mbox_put(mbox);
return rc;
diff --git a/drivers/common/cnxk/roc_npa_priv.h b/drivers/common/cnxk/roc_npa_priv.h
index 704d93d5dc..060df9ab04 100644
--- a/drivers/common/cnxk/roc_npa_priv.h
+++ b/drivers/common/cnxk/roc_npa_priv.h
@@ -50,6 +50,12 @@ struct npa_aura_lim {
struct npa_aura_attr {
int buf_type[ROC_NPA_BUF_TYPE_END];
uint16_t ref_count;
+ uint64_t nix0_bpid;
+ uint64_t nix1_bpid;
+ uint64_t shift;
+ uint64_t limit;
+ uint8_t bp_ena;
+ uint8_t bp;
};
struct dev;
--
2.25.1
next prev parent reply other threads:[~2023-08-11 8:58 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-11 8:57 [PATCH 01/31] common/cnxk: add aura ref count mechanism Nithin Dabilpuram
2023-08-11 8:57 ` Nithin Dabilpuram [this message]
2023-08-11 8:57 ` [PATCH 03/31] common/cnxk: use only user sqb slack when provided Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 04/31] common/cnxk: add workaround for CPT ctx fetch issue Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 05/31] common/cnxk: support rate limit on PFC TM tree Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 06/31] common/cnxk: fixes CGX promisc toggling Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 07/31] common/cnxk: fix xstats for different packet sizes Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 08/31] common/cnxk: disable BP on SDP link while closing SQ Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 09/31] common/cnxk: fix leak in error path Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 10/31] common/cnxk: fix different size bit operations Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 11/31] " Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 12/31] common/cnxk: remove unnecessory ROC API calls Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 13/31] common/cnxk: sync MAC addr set mailbox structure Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 14/31] common/cnxk: add API to get Rx chan count from NIX Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 15/31] common/cnxk: fix BP threshold calculation Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 16/31] common/cnxk: allow same TC on multiple RQs Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 17/31] common/cnxk: expose different params for bp config Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 18/31] common/cnxk: enable CQ stashing Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 19/31] common/cnxk: fix incorrect aura ID Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 20/31] net/cnxk: fix CQ allocation Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 21/31] net/cnxk: fix issue with GCC 4.8 Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 22/31] net/cnxk: add mapping of DMAC address indexes Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 23/31] net/cnxk: support rate limit in PFC TM tree Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 24/31] net/cnxk: move MAC address set from init to configure Nithin Dabilpuram
2023-08-11 8:57 ` [PATCH 25/31] net/cnxk: update different size bit operations Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 26/31] net/cnxk: fix uninitialized variable Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 27/31] net/cnxk: fix usage of mbuf rearm data Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 28/31] net/cnxk: fix uninitialized variable Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 29/31] net/cnxk: check returned value for null Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 30/31] net/cnxk: add flag check for extension header when used Nithin Dabilpuram
2023-08-11 8:58 ` [PATCH 31/31] net/cnxk: fixes for IPv6 header in reassembly Nithin Dabilpuram
2023-08-14 12:07 ` Jerin Jacob
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