From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 887F543095; Fri, 18 Aug 2023 11:03:07 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1030443271; Fri, 18 Aug 2023 11:02:32 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A0A0143269 for ; Fri, 18 Aug 2023 11:02:30 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 37I8bY2D014165 for ; Fri, 18 Aug 2023 02:02:29 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=J4+xRuzHwsZHxezDi+E8vYPBl9S/BHufJ38PVvhdZV0=; b=j4UnuMcgNak/lIMw+uomPtdyDtADaqrQjtxaAdrBmz2sJajRIMLxsOtFZh9kh3hfohb/ qzLQE7HX3z7WwmdWOquV1jMb4rmglHmBxeoY+26mVS2rU3IWdOOvAfih//WX8z2pkBxv 8vCJ6d8ouRRiy1TzKhJd5I84/hll6XbuywS51tzwSixllj2KVadkbMqKIX5HwX1Tkf4h PUGA65ltJN4gUETlO8rgrkhWA4sOScrcLgGQtO6N15VJpHhy3U+f0fM1h5xUaJ4WqOk/ cYrITv7q3SfWoopUrol4NzM9xun1HTi1LLQ3/ASMEmsUL3G3K8N4G9QkffoGd/kVGm83 Zg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3sj59y01uw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 18 Aug 2023 02:02:29 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Fri, 18 Aug 2023 02:02:28 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Fri, 18 Aug 2023 02:02:28 -0700 Received: from localhost.localdomain (unknown [10.28.36.157]) by maili.marvell.com (Postfix) with ESMTP id CB4AA3F7080; Fri, 18 Aug 2023 02:02:26 -0700 (PDT) From: Amit Prakash Shukla To: Vamsi Attunuru CC: , Subject: [PATCH v3 7/8] dma/cnxk: add completion ring tail wrap check Date: Fri, 18 Aug 2023 14:31:58 +0530 Message-ID: <20230818090159.2597468-7-amitprakashs@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230818090159.2597468-1-amitprakashs@marvell.com> References: <20230731121225.1545318-1-amitprakashs@marvell.com> <20230818090159.2597468-1-amitprakashs@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: vFOjopQac2M8SkEUR6OFrbTCGz5PWpcb X-Proofpoint-GUID: vFOjopQac2M8SkEUR6OFrbTCGz5PWpcb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-18_10,2023-08-17_02,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Vamsi Attunuru Adds a check to avoid tail wrap when completion desc ring is full. Also patch increase max desc size to 2048. Signed-off-by: Vamsi Attunuru --- v2: - Fix for bugs observed in v1. - Squashed few commits. v3: - Resolved review suggestions. - Code improvement. drivers/dma/cnxk/cnxk_dmadev.c | 22 ++++++++++++++++++++-- drivers/dma/cnxk/cnxk_dmadev.h | 2 +- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/dma/cnxk/cnxk_dmadev.c b/drivers/dma/cnxk/cnxk_dmadev.c index 9fb3bb264a..288606bb3d 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.c +++ b/drivers/dma/cnxk/cnxk_dmadev.c @@ -434,6 +434,11 @@ cnxk_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t d header->cn9k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn9k.nfst = 1; header->cn9k.nlst = 1; @@ -494,6 +499,11 @@ cnxk_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge header->cn9k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + /* * For inbound case, src pointers are last pointers. * For all other cases, src pointers are first pointers. @@ -561,6 +571,11 @@ cn10k_dmadev_copy(void *dev_private, uint16_t vchan, rte_iova_t src, rte_iova_t header->cn10k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn10k.nfst = 1; header->cn10k.nlst = 1; @@ -613,6 +628,11 @@ cn10k_dmadev_copy_sg(void *dev_private, uint16_t vchan, const struct rte_dma_sge header->cn10k.ptr = (uint64_t)comp_ptr; STRM_INC(dpi_conf->c_desc, tail); + if (unlikely(dpi_conf->c_desc.tail == dpi_conf->c_desc.head)) { + STRM_DEC(dpi_conf->c_desc, tail); + return -ENOSPC; + } + header->cn10k.nfst = nb_src & DPI_MAX_POINTER; header->cn10k.nlst = nb_dst & DPI_MAX_POINTER; fptr = &src[0]; @@ -695,8 +715,6 @@ cnxk_dmadev_completed_status(void *dev_private, uint16_t vchan, const uint16_t n struct cnxk_dpi_compl_s *comp_ptr; int cnt; - RTE_SET_USED(last_idx); - for (cnt = 0; cnt < nb_cpls; cnt++) { comp_ptr = c_desc->compl_ptr[c_desc->head]; status[cnt] = comp_ptr->cdata; diff --git a/drivers/dma/cnxk/cnxk_dmadev.h b/drivers/dma/cnxk/cnxk_dmadev.h index f375143b16..9c6c898d23 100644 --- a/drivers/dma/cnxk/cnxk_dmadev.h +++ b/drivers/dma/cnxk/cnxk_dmadev.h @@ -9,7 +9,7 @@ #define DPI_MAX_POINTER 15 #define STRM_INC(s, var) ((s).var = ((s).var + 1) & (s).max_cnt) #define STRM_DEC(s, var) ((s).var = ((s).var - 1) == -1 ? (s).max_cnt : ((s).var - 1)) -#define DPI_MAX_DESC 1024 +#define DPI_MAX_DESC 2048 #define DPI_MIN_DESC 2 #define MAX_VCHANS_PER_QUEUE 4 -- 2.25.1