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From: David Marchand <david.marchand@redhat.com>
To: dev@dpdk.org
Cc: thomas@monjalon.net, ferruh.yigit@amd.com, chenbo.xia@intel.com,
nipun.gupta@amd.com, bruce.richardson@intel.com,
Anatoly Burakov <anatoly.burakov@intel.com>, Gaetan Rivet <grive@u256.net>
Subject: [PATCH v2 08/15] pci: define some BAR constants
Date: Mon, 21 Aug 2023 13:35:41 +0200
Message-ID: <20230821113549.3191921-9-david.marchand@redhat.com>
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Define some PCI BAR constants and use them in existing drivers.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
---
drivers/bus/pci/linux/pci_vfio.c | 7 +++----
lib/pci/rte_pci.h | 4 ++++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c
index bf91492dd9..3f3201daf2 100644
--- a/drivers/bus/pci/linux/pci_vfio.c
+++ b/drivers/bus/pci/linux/pci_vfio.c
@@ -5,7 +5,6 @@
#include <unistd.h>
#include <string.h>
#include <fcntl.h>
-#include <linux/pci_regs.h>
#include <sys/eventfd.h>
#include <sys/socket.h>
#include <sys/ioctl.h>
@@ -427,14 +426,14 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd,
}
ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar),
- offset + PCI_BASE_ADDRESS_0 + bar_index * 4);
+ offset + RTE_PCI_BASE_ADDRESS_0 + bar_index * 4);
if (ret != sizeof(ioport_bar)) {
RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n",
- PCI_BASE_ADDRESS_0 + bar_index*4);
+ RTE_PCI_BASE_ADDRESS_0 + bar_index*4);
return -1;
}
- return (ioport_bar & PCI_BASE_ADDRESS_SPACE_IO) != 0;
+ return (ioport_bar & RTE_PCI_BASE_ADDRESS_SPACE_IO) != 0;
}
static int
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index 9eb8f85ceb..62bf87aa10 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -35,6 +35,7 @@ extern "C" {
#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
#define RTE_PCI_COMMAND 0x04 /* 16 bits */
#define RTE_PCI_STATUS 0x06 /* 16 bits */
+#define RTE_PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
#define RTE_PCI_CAPABILITY_LIST 0x34 /* 32 bits */
/* PCI Command Register (RTE_PCI_COMMAND) */
@@ -45,6 +46,9 @@ extern "C" {
/* PCI Status Register (RTE_PCI_STATUS) */
#define RTE_PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
+/* Base addresses (RTE_PCI_BASE_ADDRESS_*) */
+#define RTE_PCI_BASE_ADDRESS_SPACE_IO 0x01
+
/* Capability registers (RTE_PCI_CAPABILITY_LIST) */
#define RTE_PCI_CAP_ID_PM 0x01 /* Power Management */
#define RTE_PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
--
2.41.0