Re: [PATCH v5 3/3] power: amd power monitor support

[Tyler Retzlaff <roretzla@linux.microsoft.com>]

On Fri, Aug 18, 2023 at 02:48:42PM +0100, Bruce Richardson wrote:
> On Fri, Aug 18, 2023 at 02:25:14PM +0100, Ferruh Yigit wrote:
> > On 8/17/2023 3:18 PM, Konstantin Ananyev wrote:
> > > 
> > >>> Caution: This message originated from an External Source. Use proper caution
> > >>> when opening attachments, clicking links, or responding.
> > >>>
> > >>>
> > >>> On Wed, Aug 16, 2023 at 11:59:59AM -0700, Sivaprasad Tummala wrote:
> > >>>> mwaitx allows EPYC processors to enter a implementation dependent
> > >>>> power/performance optimized state (C1 state) for a specific period or
> > >>>> until a store to the monitored address range.
> > >>>>
> > >>>> Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@amd.com>
> > >>>> Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
> > >>>> ---
> > >>>>  lib/eal/x86/rte_power_intrinsics.c | 77
> > >>>> +++++++++++++++++++++++++-----
> > >>>>  1 file changed, 66 insertions(+), 11 deletions(-)
> > >>>>
> > >>>> diff --git a/lib/eal/x86/rte_power_intrinsics.c
> > >>>> b/lib/eal/x86/rte_power_intrinsics.c
> > >>>> index 6eb9e50807..b4754e17da 100644
> > >>>> --- a/lib/eal/x86/rte_power_intrinsics.c
> > >>>> +++ b/lib/eal/x86/rte_power_intrinsics.c
> > >>>> @@ -17,6 +17,60 @@ static struct power_wait_status {
> > >>>>       volatile void *monitor_addr; /**< NULL if not currently sleeping
> > >>>> */  } __rte_cache_aligned wait_status[RTE_MAX_LCORE];
> > >>>>
> > >>>> +/**
> > >>>> + * These functions uses UMONITOR/UMWAIT instructions and will enter C0.2
> > >>> state.
> > >>>> + * For more information about usage of these instructions, please
> > >>>> +refer to
> > >>>> + * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.
> > >>>> + */
> > >>>> +static void intel_umonitor(volatile void *addr) {
> > >>>> +     /* UMONITOR */
> > >>>> +     asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7;"
> > >>>> +                     :
> > >>>> +                     : "D"(addr));
> > >>>> +}
> > >>>> +
> > >>>> +static void intel_umwait(const uint64_t timeout) {
> > >>>> +     const uint32_t tsc_l = (uint32_t)timeout;
> > >>>> +     const uint32_t tsc_h = (uint32_t)(timeout >> 32);
> > >>>> +     /* UMWAIT */
> > >>>> +     asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7;"
> > >>>> +                     : /* ignore rflags */
> > >>>> +                     : "D"(0), /* enter C0.2 */
> > >>>> +                     "a"(tsc_l), "d"(tsc_h)); }
> > >>>
> > >>> question and perhaps Anatoly Burakov can chime in with expertise.
> > >>>
> > >>> gcc/clang have built-in intrinsics for umonitor and umwait i believe as per our other
> > >>> thread of discussion is there a benefit to also providing inline assembly over just
> > >>> using the intrinsics? I understand that the intrinsics may not exist for the monitorx
> > >>> and mwaitx below so it is probably necessary for amd.
> > >>>
> > >>> so the suggestion here is when they are available just use the intrinsics.
> > >>>
> > >>> thanks
> > >>>
> > >> The gcc built-in functions __builtin_ia32_monitorx()/__builtin_ia32_mwaitx are available only when -mmwaitx
> > >> is used specific for AMD platforms. On generic builds, these built-ins are not available and hence inline
> > >> assembly is required here.
> > > 
> > > Ok... but we can probably put them into a separate .c file that will be compiled with that specific flag?
> > > Same thing can be probably done for Intel specific instructions.
> > > In general, I think it is much more preferable to use built-ins vs inline assembly
> > > (if possible off-course). 
> > >
> > 
> > We don't compile different set of files for AMD and Intel, but there are
> > runtime checks, so putting into separate file is not much different.
> > 
> > It may be an option to always enable compiler flag (-mmwaitx), I think
> > it won't hurt other platforms but I am not sure about implications of
> > this to other platforms (what was the motivation for the compiler guys
> > to enable these build-ins with specific flag?).
> > 
> > Also this requires detecting compiler that supports 'mmwaitx' or not, etc..
> > 
> This is the biggest reason why we have in the past added support for these
> instructions via asm bytes rather than intrinsics. It takes a long time for
> end-user compilers, especially those in LTS releases, to get the necessary
> intrinsics. Consider a user running e.g. RHEL 8, who wants to take
> advantages of the latest DPDK features; they should not be required to
> upgrade their compiler - and possibly binutils/assembler - to do so.

yes, this is understood. just for clarity i'm only asking that the
intrinsics be used for intel since they are available. for amd we'll
have to use the inline asm if the older compilers don't have intrinsics.

ty

> 
> /Bruce