From: Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>
To: Kai Ji <kai.ji@intel.com>
Cc: dev@dpdk.org, stable@dpdk.org, gakhil@marvell.com,
ciara.power@intel.com,
Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>
Subject: [PATCH v1] drivers/crypto: cipher buffer alignment check
Date: Tue, 22 Aug 2023 10:46:10 +0000 [thread overview]
Message-ID: <20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com> (raw)
Cipher length alignment checked for 3DES-CBC and AES-CBC to avoid slice
hang error in QAT CPM1.8
Signed-off-by: Sivaramakrishnan VenkatX <venkatx.sivaramakrishnan@intel.com>
---
drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 21 ++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
index cab7e214c0..98504d925f 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h
@@ -10,6 +10,13 @@
#include "qat_sym_session.h"
#include "qat_sym.h"
+#define AES_OR_3DES_MISALIGNED (ctx->qat_mode == ICP_QAT_HW_CIPHER_CBC_MODE && \
+ ((((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128) || \
+ (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES192) || \
+ (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES256)) && \
+ (cipher_param->cipher_length % ICP_QAT_HW_AES_BLK_SZ)) || \
+ ((ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_3DES) && \
+ (cipher_param->cipher_length % ICP_QAT_HW_3DES_BLK_SZ))))
#define QAT_SYM_DP_GET_MAX_ENQ(q, c, n) \
RTE_MIN((q->max_inflights - q->enqueued + q->dequeued - c), n)
@@ -699,6 +706,20 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,
cipher_param->cipher_offset = ofs.ofs.cipher.head;
cipher_param->cipher_length = cipher_len;
+ /* Input cipher length alignment requirement for 3DES-CBC and AES-CBC.
+ * For 3DES-CBC cipher algo, ESP Payload size requires 8 Byte aligned.
+ * For AES-CBC cipher algo, ESP Payload size requires 16 Byte aligned.
+ * The alignment should be guaranteed by the ESP package padding field
+ * according to the RFC4303. Under this condition, QAT will pass through
+ * chain job as NULL cipher and NULL auth operation and report misalignment
+ * error detected.
+ */
+ if (AES_OR_3DES_MISALIGNED) {
+ QAT_LOG(ERR, "Input cipher length alignment error detected.\n");
+ ctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL;
+ ctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
+ cipher_param->cipher_length = 0;
+ }
qat_set_cipher_iv(cipher_param, cipher_iv, ctx->cipher_iv.length, req);
auth_param->auth_off = ofs.ofs.auth.head;
--
2.25.1
next reply other threads:[~2023-08-23 7:46 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-22 10:46 Sivaramakrishnan VenkatX [this message]
2023-09-05 11:21 ` [PATCH v2] " Sivaramakrishnan VenkatX
2023-09-19 14:41 ` Power, Ciara
2023-09-19 19:46 ` Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230822104610.954234-1-venkatx.sivaramakrishnan@intel.com \
--to=venkatx.sivaramakrishnan@intel.com \
--cc=ciara.power@intel.com \
--cc=dev@dpdk.org \
--cc=gakhil@marvell.com \
--cc=kai.ji@intel.com \
--cc=stable@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).