From: Ciara Power <ciara.power@intel.com>
To: Kai Ji <kai.ji@intel.com>
Cc: dev@dpdk.org, arkadiuszx.kusztal@intel.com,
venkatx.sivaramakrishnan@intel.com,
Ciara Power <ciara.power@intel.com>,
stable@dpdk.org
Subject: [PATCH] crypto/qat: fix raw API null algorithm digest
Date: Thu, 7 Sep 2023 15:35:53 +0000 [thread overview]
Message-ID: <20230907153553.1631938-1-ciara.power@intel.com> (raw)
QAT HW generates bytes of 0x00 digest, even when a digest of len 0 is
requested for NULL. This caused test failures when the test vector had
digest len 0, as the buffer has unexpected changed bytes.
By placing the digest into the cookie for NULL authentication,
the buffer remains unchanged as expected, and the digest
is placed to the side, as it won't be used anyway.
This fix was previously added for the main QAT code path, but it also
needs to be included for the raw API code path.
Fixes: db0e952a5c01 ("crypto/qat: add NULL capability")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
---
drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 19 ++++++++-
drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 41 +++++++++++++++++---
2 files changed, 53 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
index d25e1b2f3a..0a939161f9 100644
--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c
@@ -637,6 +637,8 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx,
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
uint32_t tail = dp_ctx->tail;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest = digest;
req = (struct icp_qat_fw_la_bulk_req *)(
(uint8_t *)tx_queue->base_addr + tail);
@@ -650,7 +652,12 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
return -1;
- enqueue_one_auth_job_gen3(ctx, cookie, req, digest, auth_iv, ofs,
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ }
+
+ enqueue_one_auth_job_gen3(ctx, cookie, req, job_digest, auth_iv, ofs,
(uint32_t)data_len);
dp_ctx->tail = tail;
@@ -672,6 +679,8 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx,
uint32_t tail;
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest = NULL;
n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num);
if (unlikely(n == 0)) {
@@ -704,7 +713,13 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
break;
- enqueue_one_auth_job_gen3(ctx, cookie, req, &vec->digest[i],
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ } else
+ job_digest = &vec->digest[i];
+
+ enqueue_one_auth_job_gen3(ctx, cookie, req, job_digest,
&vec->auth_iv[i], ofs, (uint32_t)data_len);
tail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;
}
diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
index 70938ba508..e4bcfa59e7 100644
--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c
@@ -598,6 +598,8 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx,
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
uint32_t tail = dp_ctx->tail;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest = digest;
req = (struct icp_qat_fw_la_bulk_req *)(
(uint8_t *)tx_queue->base_addr + tail);
@@ -611,8 +613,13 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
return -1;
- enqueue_one_auth_job_gen1(ctx, req, digest, auth_iv, ofs,
- (uint32_t)data_len);
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ }
+
+ enqueue_one_auth_job_gen1(ctx, req, job_digest, auth_iv, ofs,
+ (uint32_t)data_len);
dp_ctx->tail = tail;
dp_ctx->cached_enqueue++;
@@ -636,6 +643,8 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
uint32_t tail;
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest = NULL;
n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num);
if (unlikely(n == 0)) {
@@ -668,7 +677,14 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
break;
- enqueue_one_auth_job_gen1(ctx, req, &vec->digest[i],
+
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ } else
+ job_digest = &vec->digest[i];
+
+ enqueue_one_auth_job_gen1(ctx, req, job_digest,
&vec->auth_iv[i], ofs, (uint32_t)data_len);
tail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;
@@ -703,6 +719,8 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx,
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
uint32_t tail = dp_ctx->tail;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest = digest;
req = (struct icp_qat_fw_la_bulk_req *)(
(uint8_t *)tx_queue->base_addr + tail);
@@ -715,8 +733,13 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
return -1;
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ }
+
if (unlikely(enqueue_one_chain_job_gen1(ctx, req, data, n_data_vecs,
- NULL, 0, cipher_iv, digest, auth_iv, ofs,
+ NULL, 0, cipher_iv, job_digest, auth_iv, ofs,
(uint32_t)data_len)))
return -1;
@@ -743,6 +766,8 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
uint32_t tail;
struct icp_qat_fw_la_bulk_req *req;
int32_t data_len;
+ struct rte_crypto_va_iova_ptr null_digest;
+ struct rte_crypto_va_iova_ptr *job_digest;
n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num);
if (unlikely(n == 0)) {
@@ -776,10 +801,16 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,
if (unlikely(data_len < 0))
break;
+ if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) {
+ null_digest.iova = cookie->digest_null_phys_addr;
+ job_digest = &null_digest;
+ } else
+ job_digest = &vec->digest[i];
+
if (unlikely(enqueue_one_chain_job_gen1(ctx, req,
vec->src_sgl[i].vec, vec->src_sgl[i].num,
NULL, 0,
- &vec->iv[i], &vec->digest[i],
+ &vec->iv[i], job_digest,
&vec->auth_iv[i], ofs, (uint32_t)data_len)))
break;
--
2.25.1
next reply other threads:[~2023-09-07 15:36 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-07 15:35 Ciara Power [this message]
2023-09-21 8:06 ` [EXT] " Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230907153553.1631938-1-ciara.power@intel.com \
--to=ciara.power@intel.com \
--cc=arkadiuszx.kusztal@intel.com \
--cc=dev@dpdk.org \
--cc=kai.ji@intel.com \
--cc=stable@dpdk.org \
--cc=venkatx.sivaramakrishnan@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).