From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 876C44263E; Tue, 26 Sep 2023 08:00:09 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B642C40E01; Tue, 26 Sep 2023 07:59:20 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 1395140DF8 for ; Tue, 26 Sep 2023 07:59:18 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38PCsuAc032209 for ; Mon, 25 Sep 2023 22:59:18 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=/QjRF3U9k/oj8di0Az6/Ts5cFm5P1zN1604+OFiM/FI=; b=E6HfFTJJTSoKXujOwNvyNEiyQZRCiL22fnV2XQ9wZifqf+HoUGeT31TkrYymFTtQX7U5 TfNeyW5grj54K+50CSHZyIgNBdvBi5LwgMPh1q27eyr6p9X3ywFP7OWG5g6EXRRCoBON MQEHeb++XY5HIug2sEveBAiMTPRnuWE1vjF/lBsc7WFUjicE91rBfeOSVNIHJUA+Ba7+ pWPwI8hfIiw0PcLTyrzsShD4MwnMDQYEyWGJzRdW2uMMTnYVe9fZyNr71FYX/24BbvNh wdFf6lUckwSAtEgcWXHf3zK47xJXLeyW8FZTPuxakRSfUO1tqTDlhi/LM68aiO6pSUUT SQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3t9yhkynmd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 25 Sep 2023 22:59:18 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 25 Sep 2023 22:59:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Mon, 25 Sep 2023 22:59:16 -0700 Received: from hyd1554.marvell.com (unknown [10.29.57.11]) by maili.marvell.com (Postfix) with ESMTP id 048233F7070; Mon, 25 Sep 2023 22:59:13 -0700 (PDT) From: Tejasree Kondoj To: Akhil Goyal CC: Anoob Joseph , Aakash Sasidharan , Gowrishankar Muthukrishnan , Vidya Sagar Velumuri , Subject: [PATCH v2 10/15] crypto/cnxk: set PDCP chain IV offset based on FVC Date: Tue, 26 Sep 2023 11:28:42 +0530 Message-ID: <20230926055847.2707473-11-ktejasree@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230926055847.2707473-1-ktejasree@marvell.com> References: <20230926055847.2707473-1-ktejasree@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: P6ZxGeRFfFWBB_Q0NeccY7z6-IqXdV6I X-Proofpoint-ORIG-GUID: P6ZxGeRFfFWBB_Q0NeccY7z6-IqXdV6I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-26_04,2023-09-25_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Set PDCP chain IV offset based on zuc 256 firmware Signed-off-by: Tejasree Kondoj --- drivers/common/cnxk/hw/cpt.h | 4 +++- drivers/common/cnxk/roc_se.h | 3 +++ drivers/crypto/cnxk/cnxk_cryptodev_ops.c | 10 ++++++++-- drivers/crypto/cnxk/cnxk_cryptodev_ops.h | 5 +++-- drivers/crypto/cnxk/cnxk_se.h | 16 ++++++++++------ 5 files changed, 27 insertions(+), 11 deletions(-) diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h index 96a863322a..cad4ed7e79 100644 --- a/drivers/common/cnxk/hw/cpt.h +++ b/drivers/common/cnxk/hw/cpt.h @@ -78,7 +78,9 @@ union cpt_eng_caps { uint64_t __io sm4 : 1; uint64_t __io reserved_23_34 : 12; uint64_t __io sg_ver2 : 1; - uint64_t __io reserved_36_63 : 28; + uint64_t __io reserved36 : 1; + uint64_t __io pdcp_chain_zuc256 : 1; + uint64_t __io reserved_38_63 : 26; }; }; diff --git a/drivers/common/cnxk/roc_se.h b/drivers/common/cnxk/roc_se.h index 2a5abd71cf..d8cbd58c9a 100644 --- a/drivers/common/cnxk/roc_se.h +++ b/drivers/common/cnxk/roc_se.h @@ -323,6 +323,8 @@ struct roc_se_ctx { uint64_t ciph_then_auth : 1; uint64_t auth_then_ciph : 1; uint64_t eia2 : 1; + /* auth_iv_offset passed to PDCP_CHAIN opcode based on FVC bit */ + uint8_t pdcp_iv_offset; union cpt_inst_w4 template_w4; /* Below fields are accessed by hardware */ struct se_ctx_s { @@ -366,6 +368,7 @@ struct roc_se_fc_params { struct roc_se_buf_ptr meta_buf; uint8_t cipher_iv_len; uint8_t auth_iv_len; + uint8_t pdcp_iv_offset; struct roc_se_buf_ptr aad_buf; struct roc_se_buf_ptr mac_buf; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c index 99bf853234..82938c77c8 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.c +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.c @@ -484,13 +484,19 @@ is_valid_pdcp_cipher_alg(struct rte_crypto_sym_xform *c_xfrm, } static int -cnxk_sess_fill(struct rte_crypto_sym_xform *xform, struct cnxk_se_sess *sess) +cnxk_sess_fill(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xform, + struct cnxk_se_sess *sess) { struct rte_crypto_sym_xform *aead_xfrm = NULL; struct rte_crypto_sym_xform *c_xfrm = NULL; struct rte_crypto_sym_xform *a_xfrm = NULL; bool ciph_then_auth = false; + if (roc_cpt->hw_caps[CPT_ENG_TYPE_SE].pdcp_chain_zuc256) + sess->roc_se_ctx.pdcp_iv_offset = 24; + else + sess->roc_se_ctx.pdcp_iv_offset = 16; + if (xform == NULL) return -EINVAL; @@ -672,7 +678,7 @@ sym_session_configure(struct roc_cpt *roc_cpt, struct rte_crypto_sym_xform *xfor if (is_session_less) memset(sess_priv, 0, sizeof(struct cnxk_se_sess)); - ret = cnxk_sess_fill(xform, sess_priv); + ret = cnxk_sess_fill(roc_cpt, xform, sess_priv); if (ret) goto priv_put; diff --git a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h index 6ee4cbda70..3d1f9b8a48 100644 --- a/drivers/crypto/cnxk/cnxk_cryptodev_ops.h +++ b/drivers/crypto/cnxk/cnxk_cryptodev_ops.h @@ -16,8 +16,9 @@ #include "roc_errata.h" #include "roc_se.h" -#define CNXK_CPT_MIN_HEADROOM_REQ 32 -#define CNXK_CPT_MIN_TAILROOM_REQ 102 +/* Space for ctrl_word(8B), IV(48B), passthrough alignment(8B) */ +#define CNXK_CPT_MIN_HEADROOM_REQ 64 +#define CNXK_CPT_MIN_TAILROOM_REQ 102 /* Default command timeout in seconds */ #define DEFAULT_COMMAND_TIMEOUT 4 diff --git a/drivers/crypto/cnxk/cnxk_se.h b/drivers/crypto/cnxk/cnxk_se.h index b8998d401b..fdc1f3651c 100644 --- a/drivers/crypto/cnxk/cnxk_se.h +++ b/drivers/crypto/cnxk/cnxk_se.h @@ -892,7 +892,7 @@ pdcp_chain_sg1_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx, pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); /* Auth IV */ - iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + params->pdcp_iv_offset); pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); /* input data */ @@ -998,7 +998,7 @@ pdcp_chain_sg2_prep(struct roc_se_fc_params *params, struct roc_se_ctx *cpt_ctx, pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); /* Auth IV */ - iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + params->pdcp_iv_offset); pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); /* input data */ @@ -1490,11 +1490,12 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, uint32_t encr_data_len, auth_data_len, aad_len, passthr_len, pad_len, hdr_len; uint32_t encr_offset, auth_offset, iv_offset = 0; const uint8_t *auth_iv = NULL, *cipher_iv = NULL; + uint8_t pdcp_iv_off = params->pdcp_iv_offset; + const int iv_len = pdcp_iv_off * 2; uint8_t pdcp_ci_alg, pdcp_auth_alg; union cpt_inst_w4 cpt_inst_w4; struct roc_se_ctx *se_ctx; uint64_t *offset_vaddr; - const int iv_len = 32; uint64_t offset_ctrl; uint8_t pack_iv = 0; int32_t inputlen; @@ -1576,7 +1577,7 @@ cpt_pdcp_chain_alg_prep(uint32_t req_flags, uint64_t d_offs, uint64_t d_lens, iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN); pdcp_iv_copy(iv_d, cipher_iv, pdcp_ci_alg, pack_iv); - iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + 16); + iv_d = ((uint8_t *)offset_vaddr + ROC_SE_OFF_CTRL_LEN + pdcp_iv_off); pdcp_iv_copy(iv_d, auth_iv, pdcp_auth_alg, pack_iv); inst->w4.u64 = cpt_inst_w4.u64; @@ -2909,6 +2910,7 @@ fill_pdcp_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, fc_params.auth_iv_len = 0; fc_params.iv_buf = NULL; fc_params.auth_iv_buf = NULL; + fc_params.pdcp_iv_offset = sess->roc_se_ctx.pdcp_iv_offset; if (likely(sess->iv_length)) fc_params.iv_buf = rte_crypto_op_ctod_offset(cop, uint8_t *, sess->iv_offset); @@ -2995,6 +2997,7 @@ fill_pdcp_chain_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, fc_params.auth_iv_len = sess->auth_iv_length; fc_params.iv_buf = NULL; fc_params.auth_iv_buf = NULL; + fc_params.pdcp_iv_offset = sess->roc_se_ctx.pdcp_iv_offset; m_src = sym_op->m_src; m_dst = sym_op->m_dst; @@ -3197,8 +3200,9 @@ fill_digest_params(struct rte_crypto_op *cop, struct cnxk_se_sess *sess, d_offs = auth_range_off; auth_range_off = 0; params.auth_iv_len = sess->auth_iv_length; - params.auth_iv_buf = rte_crypto_op_ctod_offset( - cop, uint8_t *, sess->auth_iv_offset); + params.auth_iv_buf = + rte_crypto_op_ctod_offset(cop, uint8_t *, sess->auth_iv_offset); + params.pdcp_iv_offset = sess->roc_se_ctx.pdcp_iv_offset; if (sess->zsk_flag == ROC_SE_K_F9) { uint32_t length_in_bits, num_bytes; uint8_t *src, direction = 0; -- 2.25.1