From: Qi Zhang <qi.z.zhang@intel.com>
To: qiming.yang@intel.com
Cc: zhichaox.zeng@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>
Subject: [PATCH v5 1/5] net/ice: remove pipeline mode
Date: Tue, 26 Sep 2023 07:29:27 -0400 [thread overview]
Message-ID: <20230926112931.4191107-2-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20230926112931.4191107-1-qi.z.zhang@intel.com>
This marks the initial phase of refactoring the ice rte_flow
implementation.
The combination of switch and fdir rules within the same syntax has led
to inconvenient user experiences. Naturally, the switch filter and fdir
filter represent distinct pipeline stages with differing hardware
capabilities.
To address this, we have made the decision to assign each stage to a
separate rte_flow group. This will allow users to clearly specify their
intentions when creating a rule. Consequently, the need for a pipeline
mode can be removed.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
doc/guides/nics/ice.rst | 19 -----
drivers/net/ice/ice_ethdev.c | 8 --
drivers/net/ice/ice_ethdev.h | 2 -
drivers/net/ice/ice_fdir_filter.c | 2 +-
drivers/net/ice/ice_generic_flow.c | 120 ++++++++--------------------
drivers/net/ice/ice_generic_flow.h | 6 +-
drivers/net/ice/ice_switch_filter.c | 118 +--------------------------
7 files changed, 40 insertions(+), 235 deletions(-)
diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst
index c351c6bd74..5a47109c3f 100644
--- a/doc/guides/nics/ice.rst
+++ b/doc/guides/nics/ice.rst
@@ -90,25 +90,6 @@ Runtime Configuration
NOTE: In Safe mode, only very limited features are available, features like RSS,
checksum, fdir, tunneling ... are all disabled.
-- ``Generic Flow Pipeline Mode Support`` (default ``0``)
-
- In pipeline mode, a flow can be set at one specific stage by setting parameter
- ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with
- priority 0 located at the first pipeline stage which typically be used as a firewall
- to drop the packet on a blocklist(we called it permission stage). At this stage,
- flow rules are created for the device's exact match engine: switch. Flows with priority
- !0 located at the second stage, typically packets are classified here and be steered to
- specific queue or queue group (we called it distribution stage), At this stage, flow
- rules are created for device's flow director engine.
- For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director
- rule or a switch rule depends on its pattern/action and the resource allocation situation,
- all flows are virtually at the same pipeline stage.
- By default, generic flow API is enabled in none-pipeline mode, user can choose to
- use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``,
- for example::
-
- -a 80:00.0,pipeline-mode-support=1
-
- ``Default MAC Disable`` (default ``0``)
Disable the default MAC make the device drop all packets by default,
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 4bad39c2c1..036b068c22 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -27,7 +27,6 @@
/* devargs */
#define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
-#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
#define ICE_DEFAULT_MAC_DISABLE "default-mac-disable"
#define ICE_PROTO_XTR_ARG "proto_xtr"
#define ICE_FIELD_OFFS_ARG "field_offs"
@@ -43,7 +42,6 @@ int ice_timestamp_dynfield_offset = -1;
static const char * const ice_valid_args[] = {
ICE_SAFE_MODE_SUPPORT_ARG,
- ICE_PIPELINE_MODE_SUPPORT_ARG,
ICE_PROTO_XTR_ARG,
ICE_FIELD_OFFS_ARG,
ICE_FIELD_NAME_ARG,
@@ -2103,11 +2101,6 @@ static int ice_parse_devargs(struct rte_eth_dev *dev)
if (ret)
goto bail;
- ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
- &parse_bool, &ad->devargs.pipe_mode_support);
- if (ret)
- goto bail;
-
ret = rte_kvargs_process(kvlist, ICE_DEFAULT_MAC_DISABLE,
&parse_bool, &ad->devargs.default_mac_disable);
if (ret)
@@ -6549,7 +6542,6 @@ RTE_PMD_REGISTER_PARAM_STRING(net_ice,
ICE_HW_DEBUG_MASK_ARG "=0xXXX"
ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
- ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"
ICE_DEFAULT_MAC_DISABLE "=<0|1>"
ICE_RX_LOW_LATENCY_ARG "=<0|1>");
diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h
index 9789cb8525..1f88becd19 100644
--- a/drivers/net/ice/ice_ethdev.h
+++ b/drivers/net/ice/ice_ethdev.h
@@ -542,7 +542,6 @@ struct ice_pf {
struct ice_flow_list flow_list;
rte_spinlock_t flow_ops_lock;
struct ice_parser_list rss_parser_list;
- struct ice_parser_list perm_parser_list;
struct ice_parser_list dist_parser_list;
bool init_link_up;
uint64_t old_rx_bytes;
@@ -563,7 +562,6 @@ struct ice_devargs {
int rx_low_latency;
int safe_mode_support;
uint8_t proto_xtr_dflt;
- int pipe_mode_support;
uint8_t default_mac_disable;
uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
uint8_t pin_idx;
diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c
index e8842bc242..e9ee5a57d6 100644
--- a/drivers/net/ice/ice_fdir_filter.c
+++ b/drivers/net/ice/ice_fdir_filter.c
@@ -2467,7 +2467,7 @@ ice_fdir_parse(struct ice_adapter *ad,
item = ice_search_pattern_match_item(ad, pattern, array, array_len,
error);
- if (!ad->devargs.pipe_mode_support && priority >= 1)
+ if (priority >= 1)
return -rte_errno;
if (!item)
diff --git a/drivers/net/ice/ice_generic_flow.c b/drivers/net/ice/ice_generic_flow.c
index 91bf1d6fcb..6695457bbd 100644
--- a/drivers/net/ice/ice_generic_flow.c
+++ b/drivers/net/ice/ice_generic_flow.c
@@ -18,16 +18,6 @@
#include "ice_ethdev.h"
#include "ice_generic_flow.h"
-/**
- * Non-pipeline mode, fdir and switch both used as distributor,
- * fdir used first, switch used as fdir's backup.
- */
-#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY 0
-/*Pipeline mode, switch used at permission stage*/
-#define ICE_FLOW_CLASSIFY_STAGE_PERMISSION 1
-/*Pipeline mode, fdir used at distributor stage*/
-#define ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR 2
-
#define ICE_FLOW_ENGINE_DISABLED(mask, type) ((mask) & BIT(type))
static struct ice_engine_list engine_list =
@@ -1829,7 +1819,6 @@ ice_flow_init(struct ice_adapter *ad)
TAILQ_INIT(&pf->flow_list);
TAILQ_INIT(&pf->rss_parser_list);
- TAILQ_INIT(&pf->perm_parser_list);
TAILQ_INIT(&pf->dist_parser_list);
rte_spinlock_init(&pf->flow_ops_lock);
@@ -1898,11 +1887,6 @@ ice_flow_uninit(struct ice_adapter *ad)
rte_free(p_parser);
}
- while ((p_parser = TAILQ_FIRST(&pf->perm_parser_list))) {
- TAILQ_REMOVE(&pf->perm_parser_list, p_parser, node);
- rte_free(p_parser);
- }
-
while ((p_parser = TAILQ_FIRST(&pf->dist_parser_list))) {
TAILQ_REMOVE(&pf->dist_parser_list, p_parser, node);
rte_free(p_parser);
@@ -1925,9 +1909,6 @@ ice_get_parser_list(struct ice_flow_parser *parser,
case ICE_FLOW_STAGE_RSS:
list = &pf->rss_parser_list;
break;
- case ICE_FLOW_STAGE_PERMISSION:
- list = &pf->perm_parser_list;
- break;
case ICE_FLOW_STAGE_DISTRIBUTOR:
list = &pf->dist_parser_list;
break;
@@ -1958,38 +1939,34 @@ ice_register_parser(struct ice_flow_parser *parser,
if (list == NULL)
return -EINVAL;
- if (ad->devargs.pipe_mode_support) {
- TAILQ_INSERT_TAIL(list, parser_node, node);
- } else {
- if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) {
- RTE_TAILQ_FOREACH_SAFE(existing_node, list,
- node, temp) {
- if (existing_node->parser->engine->type ==
- ICE_FLOW_ENGINE_ACL) {
- TAILQ_INSERT_AFTER(list, existing_node,
- parser_node, node);
- goto DONE;
- }
+ if (parser->engine->type == ICE_FLOW_ENGINE_SWITCH) {
+ RTE_TAILQ_FOREACH_SAFE(existing_node, list,
+ node, temp) {
+ if (existing_node->parser->engine->type ==
+ ICE_FLOW_ENGINE_ACL) {
+ TAILQ_INSERT_AFTER(list, existing_node,
+ parser_node, node);
+ goto DONE;
}
- TAILQ_INSERT_HEAD(list, parser_node, node);
- } else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) {
- RTE_TAILQ_FOREACH_SAFE(existing_node, list,
- node, temp) {
- if (existing_node->parser->engine->type ==
- ICE_FLOW_ENGINE_SWITCH) {
- TAILQ_INSERT_AFTER(list, existing_node,
- parser_node, node);
- goto DONE;
- }
+ }
+ TAILQ_INSERT_HEAD(list, parser_node, node);
+ } else if (parser->engine->type == ICE_FLOW_ENGINE_FDIR) {
+ RTE_TAILQ_FOREACH_SAFE(existing_node, list,
+ node, temp) {
+ if (existing_node->parser->engine->type ==
+ ICE_FLOW_ENGINE_SWITCH) {
+ TAILQ_INSERT_AFTER(list, existing_node,
+ parser_node, node);
+ goto DONE;
}
- TAILQ_INSERT_HEAD(list, parser_node, node);
- } else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) {
- TAILQ_INSERT_TAIL(list, parser_node, node);
- } else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) {
- TAILQ_INSERT_HEAD(list, parser_node, node);
- } else {
- return -EINVAL;
}
+ TAILQ_INSERT_HEAD(list, parser_node, node);
+ } else if (parser->engine->type == ICE_FLOW_ENGINE_HASH) {
+ TAILQ_INSERT_TAIL(list, parser_node, node);
+ } else if (parser->engine->type == ICE_FLOW_ENGINE_ACL) {
+ TAILQ_INSERT_HEAD(list, parser_node, node);
+ } else {
+ return -EINVAL;
}
DONE:
return 0;
@@ -2016,10 +1993,8 @@ ice_unregister_parser(struct ice_flow_parser *parser,
}
static int
-ice_flow_valid_attr(struct ice_adapter *ad,
- const struct rte_flow_attr *attr,
- int *ice_pipeline_stage,
- struct rte_flow_error *error)
+ice_flow_valid_attr(const struct rte_flow_attr *attr,
+ struct rte_flow_error *error)
{
/* Must be input direction */
if (!attr->ingress) {
@@ -2045,23 +2020,11 @@ ice_flow_valid_attr(struct ice_adapter *ad,
return -rte_errno;
}
- /* Check pipeline mode support to set classification stage */
- if (ad->devargs.pipe_mode_support) {
- if (attr->priority == 0)
- *ice_pipeline_stage =
- ICE_FLOW_CLASSIFY_STAGE_PERMISSION;
- else
- *ice_pipeline_stage =
- ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR;
- } else {
- *ice_pipeline_stage =
- ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY;
- if (attr->priority > 1) {
- rte_flow_error_set(error, EINVAL,
- RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
- attr, "Only support priority 0 and 1.");
- return -rte_errno;
- }
+ if (attr->priority > 1) {
+ rte_flow_error_set(error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
+ attr, "Only support priority 0 and 1.");
+ return -rte_errno;
}
/* Not supported */
@@ -2407,7 +2370,6 @@ ice_flow_process_filter(struct rte_eth_dev *dev,
struct ice_adapter *ad =
ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
- int ice_pipeline_stage = 0;
if (!pattern) {
rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
@@ -2429,7 +2391,7 @@ ice_flow_process_filter(struct rte_eth_dev *dev,
return -rte_errno;
}
- ret = ice_flow_valid_attr(ad, attr, &ice_pipeline_stage, error);
+ ret = ice_flow_valid_attr(attr, error);
if (ret)
return ret;
@@ -2438,20 +2400,8 @@ ice_flow_process_filter(struct rte_eth_dev *dev,
if (*engine != NULL)
return 0;
- switch (ice_pipeline_stage) {
- case ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY:
- case ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR:
- *engine = ice_parse_engine(ad, flow, &pf->dist_parser_list,
- attr->priority, pattern, actions, error);
- break;
- case ICE_FLOW_CLASSIFY_STAGE_PERMISSION:
- *engine = ice_parse_engine(ad, flow, &pf->perm_parser_list,
- attr->priority, pattern, actions, error);
- break;
- default:
- return -EINVAL;
- }
-
+ *engine = ice_parse_engine(ad, flow, &pf->dist_parser_list,
+ attr->priority, pattern, actions, error);
if (*engine == NULL)
return -EINVAL;
diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h
index 11f51a5c15..471f255bd6 100644
--- a/drivers/net/ice/ice_generic_flow.h
+++ b/drivers/net/ice/ice_generic_flow.h
@@ -418,15 +418,13 @@ enum ice_flow_engine_type {
};
/**
- * classification stages.
- * for non-pipeline mode, we have two classification stages: Distributor/RSS
- * for pipeline-mode we have three classification stages:
+ * Classification stages.
+ * We have two classification stages: Distributor/RSS
* Permission/Distributor/RSS
*/
enum ice_flow_classification_stage {
ICE_FLOW_STAGE_NONE = 0,
ICE_FLOW_STAGE_RSS,
- ICE_FLOW_STAGE_PERMISSION,
ICE_FLOW_STAGE_DISTRIBUTOR,
ICE_FLOW_STAGE_MAX,
};
diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c
index 110d8895fe..88d599068f 100644
--- a/drivers/net/ice/ice_switch_filter.c
+++ b/drivers/net/ice/ice_switch_filter.c
@@ -202,7 +202,6 @@ struct ice_switch_filter_conf {
};
static struct ice_flow_parser ice_switch_dist_parser;
-static struct ice_flow_parser ice_switch_perm_parser;
static struct
ice_pattern_match_item ice_switch_pattern_dist_list[] = {
@@ -288,90 +287,6 @@ ice_pattern_match_item ice_switch_pattern_dist_list[] = {
{pattern_eth_ipv6_gtpu_eh_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE},
};
-static struct
-ice_pattern_match_item ice_switch_pattern_perm_list[] = {
- {pattern_any, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_ethertype, ICE_SW_INSET_ETHER, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_ethertype_vlan, ICE_SW_INSET_MAC_VLAN, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_ethertype_qinq, ICE_SW_INSET_MAC_QINQ, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_arp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4, ICE_SW_INSET_MAC_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_udp, ICE_SW_INSET_MAC_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_tcp, ICE_SW_INSET_MAC_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6, ICE_SW_INSET_MAC_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_udp, ICE_SW_INSET_MAC_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_tcp, ICE_SW_INSET_MAC_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_udp_vxlan_eth_ipv4, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv4_udp_vxlan_eth_ipv4_udp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_udp_vxlan_eth_ipv4_tcp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv4_nvgre_eth_ipv4, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv4_nvgre_eth_ipv4_udp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_nvgre_eth_ipv4_tcp, ICE_INSET_NONE, ICE_SW_INSET_PERM_TUNNEL_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv4_tcp, ICE_SW_INSET_MAC_PPPOE_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv4_udp, ICE_SW_INSET_MAC_PPPOE_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv6, ICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv6_tcp, ICE_SW_INSET_MAC_PPPOE_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_pppoes_ipv6_udp, ICE_SW_INSET_MAC_PPPOE_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv4_tcp, ICE_SW_INSET_MAC_PPPOE_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv4_udp, ICE_SW_INSET_MAC_PPPOE_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv6, ICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv6_tcp, ICE_SW_INSET_MAC_PPPOE_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_vlan_pppoes_ipv6_udp, ICE_SW_INSET_MAC_PPPOE_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_esp, ICE_SW_INSET_MAC_IPV4_ESP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_udp_esp, ICE_SW_INSET_MAC_IPV4_ESP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_esp, ICE_SW_INSET_MAC_IPV6_ESP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_udp_esp, ICE_SW_INSET_MAC_IPV6_ESP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_ah, ICE_SW_INSET_MAC_IPV4_AH, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_ah, ICE_SW_INSET_MAC_IPV6_AH, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_udp_ah, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_l2tp, ICE_SW_INSET_MAC_IPV4_L2TP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_l2tp, ICE_SW_INSET_MAC_IPV6_L2TP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_pfcp, ICE_INSET_NONE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv4, ICE_SW_INSET_MAC_QINQ_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv4_tcp, ICE_SW_INSET_MAC_QINQ_IPV4_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv4_udp, ICE_SW_INSET_MAC_QINQ_IPV4_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv6, ICE_SW_INSET_MAC_QINQ_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv6_tcp, ICE_SW_INSET_MAC_QINQ_IPV6_TCP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_ipv6_udp, ICE_SW_INSET_MAC_QINQ_IPV6_UDP, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_pppoes, ICE_SW_INSET_MAC_PPPOE, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_pppoes_proto, ICE_SW_INSET_MAC_PPPOE_PROTO, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_pppoes_ipv4, ICE_SW_INSET_MAC_PPPOE_IPV4, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_qinq_pppoes_ipv6, ICE_SW_INSET_MAC_PPPOE_IPV6, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu, ICE_SW_INSET_MAC_IPV4_GTPU, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu, ICE_SW_INSET_MAC_IPV6_GTPU, ICE_INSET_NONE, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv4, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv4, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv4_udp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv4_udp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv4_tcp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv4_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv6, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv6, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv6_udp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv6_udp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv4_gtpu_eh_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv4, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv4, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv4_udp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv4_udp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv4_tcp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv4_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV4_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv6, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv6, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv6_udp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv6_udp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_UDP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE},
- {pattern_eth_ipv6_gtpu_eh_ipv6_tcp, ICE_SW_INSET_MAC_GTPU_EH_OUTER, ICE_SW_INSET_GTPU_IPV6_TCP, ICE_INSET_NONE},
-};
-
static int
ice_switch_create(struct ice_adapter *ad,
struct rte_flow *flow,
@@ -2139,33 +2054,13 @@ ice_switch_redirect(struct ice_adapter *ad,
static int
ice_switch_init(struct ice_adapter *ad)
{
- int ret = 0;
- struct ice_flow_parser *dist_parser;
- struct ice_flow_parser *perm_parser;
-
- if (ad->devargs.pipe_mode_support) {
- perm_parser = &ice_switch_perm_parser;
- ret = ice_register_parser(perm_parser, ad);
- } else {
- dist_parser = &ice_switch_dist_parser;
- ret = ice_register_parser(dist_parser, ad);
- }
- return ret;
+ return ice_register_parser(&ice_switch_dist_parser, ad);
}
static void
ice_switch_uninit(struct ice_adapter *ad)
{
- struct ice_flow_parser *dist_parser;
- struct ice_flow_parser *perm_parser;
-
- if (ad->devargs.pipe_mode_support) {
- perm_parser = &ice_switch_perm_parser;
- ice_unregister_parser(perm_parser, ad);
- } else {
- dist_parser = &ice_switch_dist_parser;
- ice_unregister_parser(dist_parser, ad);
- }
+ ice_unregister_parser(&ice_switch_dist_parser, ad);
}
static struct
@@ -2189,15 +2084,6 @@ ice_flow_parser ice_switch_dist_parser = {
.stage = ICE_FLOW_STAGE_DISTRIBUTOR,
};
-static struct
-ice_flow_parser ice_switch_perm_parser = {
- .engine = &ice_switch_engine,
- .array = ice_switch_pattern_perm_list,
- .array_len = RTE_DIM(ice_switch_pattern_perm_list),
- .parse_pattern_action = ice_switch_parse_pattern_action,
- .stage = ICE_FLOW_STAGE_PERMISSION,
-};
-
RTE_INIT(ice_sw_engine_init)
{
struct ice_flow_engine *engine = &ice_switch_engine;
--
2.31.1
next prev parent reply other threads:[~2023-09-26 3:09 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-14 20:26 [PATCH 0/2] refactor rte_flow Qi Zhang
2023-08-14 20:26 ` [PATCH 1/2] net/ice: remove pipeline mode Qi Zhang
2023-08-14 20:26 ` [PATCH 2/2] net/ice: map group to pipeline stage Qi Zhang
2023-09-11 16:51 ` [PATCH v2 0/2] refactor rte_flow Qi Zhang
2023-09-11 16:51 ` [PATCH v2 1/2] net/ice: remove pipeline mode Qi Zhang
2023-09-11 16:51 ` [PATCH v2 2/2] net/ice: map group to pipeline stage Qi Zhang
2023-09-12 10:00 ` [PATCH v3 0/5] refactor rte_flow Qi Zhang
2023-09-12 10:00 ` [PATCH v3 1/5] net/ice: remove pipeline mode Qi Zhang
2023-09-12 10:00 ` [PATCH v3 2/5] net/ice: refine flow engine disabling Qi Zhang
2023-09-12 10:00 ` [PATCH v3 3/5] net/ice: map group to pipeline stage Qi Zhang
2023-09-12 10:00 ` [PATCH v3 4/5] net/ice: refine supported flow pattern name Qi Zhang
2023-09-12 10:00 ` [PATCH v3 5/5] doc: add generic flow doc for ice PMD Qi Zhang
2023-09-25 10:33 ` [PATCH v4 0/5] net/ice: refactor rte_flow Qi Zhang
2023-09-25 10:33 ` [PATCH v4 1/5] net/ice: remove pipeline mode Qi Zhang
2023-09-25 10:33 ` [PATCH v4 2/5] net/ice: refine flow engine disabling Qi Zhang
2023-09-25 10:33 ` [PATCH v4 3/5] net/ice: map group to pipeline stage Qi Zhang
2023-09-25 10:33 ` [PATCH v4 4/5] net/ice: refine supported flow pattern name Qi Zhang
2023-09-25 10:33 ` [PATCH v4 5/5] doc: add generic flow doc for ice PMD Qi Zhang
2023-09-26 11:29 ` [PATCH v5 0/5] net/ice: refactor rte_flow Qi Zhang
2023-09-26 11:29 ` Qi Zhang [this message]
2023-09-26 11:29 ` [PATCH v5 2/5] net/ice: refine flow engine disabling Qi Zhang
2023-09-26 11:29 ` [PATCH v5 3/5] net/ice: map group to pipeline stage Qi Zhang
2023-09-26 11:29 ` [PATCH v5 4/5] net/ice: refine supported flow pattern name Qi Zhang
2023-09-26 11:29 ` [PATCH v5 5/5] doc: add generic flow doc for ice PMD Qi Zhang
2023-09-27 2:42 ` Zeng, ZhichaoX
2023-09-27 3:08 ` Zhang, Qi Z
2023-10-13 13:17 ` Thomas Monjalon
2023-10-26 10:43 ` Zhang, Qi Z
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