From: Alexander Kozyrev <akozyrev@nvidia.com>
To: <dev@dpdk.org>
Cc: <orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,
<valex@nvidia.com>, <suanmingm@nvidia.com>,
<viacheslavo@nvidia.com>
Subject: [PATCH 2/5] net/mlx5/hws: add support for fragmented ptype match
Date: Mon, 9 Oct 2023 19:36:14 +0300 [thread overview]
Message-ID: <20231009163617.3999365-3-akozyrev@nvidia.com> (raw)
In-Reply-To: <20231009163617.3999365-1-akozyrev@nvidia.com>
Expand packet type matching with support of the
Fragmented IP (Internet Protocol) packet type.
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 74 +++++++++++++++++++--------
drivers/net/mlx5/hws/mlx5dr_definer.h | 2 +
2 files changed, 56 insertions(+), 20 deletions(-)
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index e3f4a3c0a8..b2c0655790 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -361,6 +361,19 @@ mlx5dr_definer_ptype_l4_ext_set(struct mlx5dr_definer_fc *fc,
DR_SET(tag, l4_type, fc->byte_off, fc->bit_off, fc->bit_mask);
}
+static void
+mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc,
+ const void *item_spec,
+ uint8_t *tag)
+{
+ bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I);
+ const struct rte_flow_item_ptype *v = item_spec;
+ uint32_t packet_type = v->packet_type &
+ (inner ? RTE_PTYPE_INNER_L4_FRAG : RTE_PTYPE_L4_FRAG);
+
+ DR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
static void
mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
const void *item_spec,
@@ -1828,31 +1841,52 @@ mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd,
}
if (m->packet_type & RTE_PTYPE_L4_MASK) {
- fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];
- fc->item_idx = item_idx;
- fc->tag_set = &mlx5dr_definer_ptype_l4_set;
- fc->tag_mask_set = &mlx5dr_definer_ones_set;
- DR_CALC_SET(fc, eth_l2, l4_type_bwc, false);
+ /*
+ * Fragmented IP (Internet Protocol) packet type.
+ * Cannot be combined with Layer 4 Types (TCP/UDP).
+ * The exact value must be specified in the mask.
+ */
+ if (m->packet_type == RTE_PTYPE_L4_FRAG) {
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, false)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_frag_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, ip_fragmented, false);
+ } else {
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_l4_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, l4_type_bwc, false);
- fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, false)];
- fc->item_idx = item_idx;
- fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set;
- fc->tag_mask_set = &mlx5dr_definer_ones_set;
- DR_CALC_SET(fc, eth_l2, l4_type, false);
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, false)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, l4_type, false);
+ }
}
if (m->packet_type & RTE_PTYPE_INNER_L4_MASK) {
- fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];
- fc->item_idx = item_idx;
- fc->tag_set = &mlx5dr_definer_ptype_l4_set;
- fc->tag_mask_set = &mlx5dr_definer_ones_set;
- DR_CALC_SET(fc, eth_l2, l4_type_bwc, true);
+ if (m->packet_type == RTE_PTYPE_INNER_L4_FRAG) {
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, true)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_frag_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, ip_fragmented, true);
+ } else {
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_l4_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, l4_type_bwc, true);
- fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, true)];
- fc->item_idx = item_idx;
- fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set;
- fc->tag_mask_set = &mlx5dr_definer_ones_set;
- DR_CALC_SET(fc, eth_l2, l4_type, true);
+ fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4_EXT, true)];
+ fc->item_idx = item_idx;
+ fc->tag_set = &mlx5dr_definer_ptype_l4_ext_set;
+ fc->tag_mask_set = &mlx5dr_definer_ones_set;
+ DR_CALC_SET(fc, eth_l2, l4_type, true);
+ }
}
return 0;
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index 6b02161e02..e87b4108f9 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -144,6 +144,8 @@ enum mlx5dr_definer_fname {
MLX5DR_DEFINER_FNAME_PTYPE_L4_I,
MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_O,
MLX5DR_DEFINER_FNAME_PTYPE_L4_EXT_I,
+ MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
+ MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
MLX5DR_DEFINER_FNAME_MAX,
};
--
2.18.2
next prev parent reply other threads:[~2023-10-09 16:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 16:36 [PATCH 0/5] ptype matching support in mlx5 Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 1/5] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-09 16:36 ` Alexander Kozyrev [this message]
2023-10-09 16:36 ` [PATCH 3/5] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 4/5] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 5/5] net/mlx5/hws: fix integrity bits level Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 0/7] ptype matching support in mlx5 Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 1/7] ethdev: fix ESP packet type description Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 2/7] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 3/7] net/mlx5/hws: add support for fragmented ptype match Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 4/7] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 5/7] doc: add packet type matching item to release notes Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 6/7] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 7/7] net/mlx5/hws: fix integrity bits level Alexander Kozyrev
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