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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000EDD4.mail.protection.outlook.com (10.167.241.208) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.22 via Frontend Transport; Wed, 11 Oct 2023 06:42:26 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 10 Oct 2023 23:42:14 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 10 Oct 2023 23:42:12 -0700 From: Jiawei Wang To: , , CC: , Subject: [PATCH] net/mlx5: support no host PF configuration Date: Wed, 11 Oct 2023 09:41:53 +0300 Message-ID: <20231011064153.46486-1-jiaweiw@nvidia.com> X-Mailer: git-send-email 2.18.1 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|MW4PR12MB6708:EE_ X-MS-Office365-Filtering-Correlation-Id: e0ee9025-7f26-49b4-e29d-08dbca253b79 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Oct 2023 06:42:26.2095 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0ee9025-7f26-49b4-e29d-08dbca253b79 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6708 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Xueming Li In BlueField, a new firmware configuration option NUM_OF_PF=0 disables PF on the x86 host side, no HPF on the ARM side, and the only RDMA port on the ARM side is the bonding device(PF0). A device probe with devargs of representor=pf[0-1]vf[...] will probe PF0 and PF1 one by one, and it's possible that PF1 device scan results in no switch ports. This patch supports the new configuration by allowing a PF scan with empty switch ports. Signed-off-by: Xueming Li Signed-off-by: Jiawei Wang --- drivers/net/mlx5/linux/mlx5_os.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index d5ef695e6d..75f53ade8e 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -2195,13 +2195,6 @@ mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev, list[ns].info.master)) ns++; } - if (!ns) { - DRV_LOG(ERR, - "Unable to recognize master/representors on the IB device with multiple ports."); - rte_errno = ENOENT; - ret = -rte_errno; - goto exit; - } } else { /* * The existence of several matching entries (nd > 1) means -- 2.18.1