From: Vamsi Attunuru <vattunuru@marvell.com>
To: <dev@dpdk.org>, <jerinj@marvell.com>
Cc: <sthotton@marvell.com>
Subject: [PATCH v5 1/3] net/octeon_ep: support 32B IQ descriptor size
Date: Wed, 18 Oct 2023 01:07:23 -0700 [thread overview]
Message-ID: <20231018080725.613579-2-vattunuru@marvell.com> (raw)
In-Reply-To: <20231018080725.613579-1-vattunuru@marvell.com>
From: Shijith Thotton <sthotton@marvell.com>
Update input queue setup to consider descriptor size in driver conf.
The default instruction size for otx2 and cnxk devices has been updated
to 32 bytes.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
---
drivers/net/octeon_ep/cnxk_ep_vf.c | 10 +++++++++-
drivers/net/octeon_ep/otx2_ep_vf.c | 10 +++++++++-
drivers/net/octeon_ep/otx_ep_common.h | 4 ++++
drivers/net/octeon_ep/otx_ep_vf.c | 8 ++++++++
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/net/octeon_ep/cnxk_ep_vf.c b/drivers/net/octeon_ep/cnxk_ep_vf.c
index 92c2d2ca5c..7b3669fe0c 100644
--- a/drivers/net/octeon_ep/cnxk_ep_vf.c
+++ b/drivers/net/octeon_ep/cnxk_ep_vf.c
@@ -106,6 +106,14 @@ cnxk_ep_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
return -EIO;
}
+ /* Configure input queue instruction size. */
+ if (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR)
+ reg_val &= ~(CNXK_EP_R_IN_CTL_IS_64B);
+ else
+ reg_val |= CNXK_EP_R_IN_CTL_IS_64B;
+ oct_ep_write64(reg_val, otx_ep->hw_addr + CNXK_EP_R_IN_CONTROL(iq_no));
+ iq->desc_size = otx_ep->conf->iq.instr_type;
+
/* Write the start of the input queue's ring and its size */
oct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_BADDR(iq_no));
oct_ep_write64(iq->nb_desc, otx_ep->hw_addr + CNXK_EP_R_IN_INSTR_RSIZE(iq_no));
@@ -354,7 +362,7 @@ static const struct otx_ep_config default_cnxk_ep_conf = {
/* IQ attributes */
.iq = {
.max_iqs = OTX_EP_CFG_IO_QUEUES,
- .instr_type = OTX_EP_64BYTE_INSTR,
+ .instr_type = OTX_EP_32BYTE_INSTR,
.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
OTX_EP_CFG_IO_QUEUES),
},
diff --git a/drivers/net/octeon_ep/otx2_ep_vf.c b/drivers/net/octeon_ep/otx2_ep_vf.c
index ced3a415a5..f72b8d25d7 100644
--- a/drivers/net/octeon_ep/otx2_ep_vf.c
+++ b/drivers/net/octeon_ep/otx2_ep_vf.c
@@ -256,6 +256,14 @@ otx2_vf_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
return -EIO;
}
+ /* Configure input queue instruction size. */
+ if (otx_ep->conf->iq.instr_type == OTX_EP_32BYTE_INSTR)
+ reg_val &= ~(SDP_VF_R_IN_CTL_IS_64B);
+ else
+ reg_val |= SDP_VF_R_IN_CTL_IS_64B;
+ oct_ep_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_CONTROL(iq_no));
+ iq->desc_size = otx_ep->conf->iq.instr_type;
+
/* Write the start of the input queue's ring and its size */
oct_ep_write64(iq->base_addr_dma, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_BADDR(iq_no));
oct_ep_write64(iq->nb_desc, otx_ep->hw_addr + SDP_VF_R_IN_INSTR_RSIZE(iq_no));
@@ -500,7 +508,7 @@ static const struct otx_ep_config default_otx2_ep_conf = {
/* IQ attributes */
.iq = {
.max_iqs = OTX_EP_CFG_IO_QUEUES,
- .instr_type = OTX_EP_64BYTE_INSTR,
+ .instr_type = OTX_EP_32BYTE_INSTR,
.pending_list_size = (OTX_EP_MAX_IQ_DESCRIPTORS *
OTX_EP_CFG_IO_QUEUES),
},
diff --git a/drivers/net/octeon_ep/otx_ep_common.h b/drivers/net/octeon_ep/otx_ep_common.h
index c150cbe619..90e059cad0 100644
--- a/drivers/net/octeon_ep/otx_ep_common.h
+++ b/drivers/net/octeon_ep/otx_ep_common.h
@@ -11,6 +11,7 @@
#define OTX_EP_MAX_RINGS_PER_VF (8)
#define OTX_EP_CFG_IO_QUEUES OTX_EP_MAX_RINGS_PER_VF
+#define OTX_EP_32BYTE_INSTR (32)
#define OTX_EP_64BYTE_INSTR (64)
/*
* Backpressure for SDP is configured on Octeon, and the minimum queue sizes
@@ -215,6 +216,9 @@ struct otx_ep_instr_queue {
/* Number of descriptors in this ring. */
uint32_t nb_desc;
+ /* Size of the descriptor. */
+ uint8_t desc_size;
+
/* Input ring index, where the driver should write the next packet */
uint32_t host_write_index;
diff --git a/drivers/net/octeon_ep/otx_ep_vf.c b/drivers/net/octeon_ep/otx_ep_vf.c
index 4f3538146b..236b7a874c 100644
--- a/drivers/net/octeon_ep/otx_ep_vf.c
+++ b/drivers/net/octeon_ep/otx_ep_vf.c
@@ -120,6 +120,14 @@ otx_ep_setup_iq_regs(struct otx_ep_device *otx_ep, uint32_t iq_no)
return -EIO;
}
+ /* Configure input queue instruction size. */
+ if (iq->desc_size == OTX_EP_32BYTE_INSTR)
+ reg_val &= ~(OTX_EP_R_IN_CTL_IS_64B);
+ else
+ reg_val |= OTX_EP_R_IN_CTL_IS_64B;
+ oct_ep_write64(reg_val, otx_ep->hw_addr + OTX_EP_R_IN_CONTROL(iq_no));
+ iq->desc_size = otx_ep->conf->iq.instr_type;
+
/* Write the start of the input queue's ring and its size */
otx_ep_write64(iq->base_addr_dma, otx_ep->hw_addr,
OTX_EP_R_IN_INSTR_BADDR(iq_no));
--
2.25.1
next prev parent reply other threads:[~2023-10-18 8:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 1:50 [PATCH 0/3] rewrite fastpath routines Vamsi Attunuru
2023-10-11 1:50 ` [PATCH 1/3] net/octeon_ep: support 32B IQ descriptor size Vamsi Attunuru
2023-10-11 1:50 ` [PATCH 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-11 1:50 ` [PATCH 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-11 8:36 ` [PATCH v2 0/3] rewrite " Vamsi Attunuru
2023-10-11 8:36 ` [PATCH v2 1/3] net/octeon_ep: support 32B IQ descriptor size Vamsi Attunuru
2023-10-11 8:36 ` [PATCH v2 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-11 8:36 ` [PATCH v2 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-11 12:53 ` [PATCH v3 0/3] rewrite " Vamsi Attunuru
2023-10-11 12:53 ` [PATCH v3 1/3] net/octeon_ep: support 32B IQ descriptor size Vamsi Attunuru
2023-10-11 12:53 ` [PATCH v3 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-11 12:53 ` [PATCH v3 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-12 6:23 ` [PATCH v4 0/3] rewrite " Vamsi Attunuru
2023-10-12 6:23 ` [PATCH v4 1/3] net/octeon_ep: support 32B IQ descriptor size Vamsi Attunuru
2023-10-12 6:23 ` [PATCH v4 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-12 6:23 ` [PATCH v4 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-18 3:48 ` Jerin Jacob
2023-10-18 8:07 ` [PATCH v5 0/3] rewrite " Vamsi Attunuru
2023-10-18 8:07 ` Vamsi Attunuru [this message]
2023-10-18 8:07 ` [PATCH v5 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-18 8:07 ` [PATCH v5 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-18 11:14 ` [PATCH v6 0/3] rewrite " Vamsi Attunuru
2023-10-18 11:14 ` [PATCH v6 1/3] net/octeon_ep: support 32B IQ descriptor size Vamsi Attunuru
2023-10-18 11:14 ` [PATCH v6 2/3] net/octeon_ep: clean up receive routine Vamsi Attunuru
2023-10-18 11:14 ` [PATCH v6 3/3] net/octeon_ep: add new fastpath routines Vamsi Attunuru
2023-10-19 3:03 ` Jerin Jacob
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