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From: Alexander Kozyrev <akozyrev@nvidia.com>
To: <dev@dpdk.org>
Cc: <orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,
	<valex@nvidia.com>, <suanmingm@nvidia.com>,
	<viacheslavo@nvidia.com>
Subject: [PATCH v2 3/7] net/mlx5/hws: add support for fragmented ptype match
Date: Tue, 24 Oct 2023 00:07:03 +0300	[thread overview]
Message-ID: <20231023210707.1344241-4-akozyrev@nvidia.com> (raw)
In-Reply-To: <20231023210707.1344241-1-akozyrev@nvidia.com>

Expand packet type matching with support of the
Fragmented IP (Internet Protocol) packet type.

Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 54 ++++++++++++++++++++++-----
 drivers/net/mlx5/hws/mlx5dr_definer.h |  2 +
 2 files changed, 46 insertions(+), 10 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 8d846984e7..0e1035c6bd 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -357,6 +357,19 @@ mlx5dr_definer_ptype_tunnel_set(struct mlx5dr_definer_fc *fc,
 	DR_SET(tag, tun_type, fc->byte_off, fc->bit_off, fc->bit_mask);
 }
 
+static void
+mlx5dr_definer_ptype_frag_set(struct mlx5dr_definer_fc *fc,
+			      const void *item_spec,
+			      uint8_t *tag)
+{
+	bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I);
+	const struct rte_flow_item_ptype *v = item_spec;
+	uint32_t packet_type = v->packet_type &
+		(inner ? RTE_PTYPE_INNER_L4_FRAG : RTE_PTYPE_L4_FRAG);
+
+	DR_SET(tag, !!packet_type, fc->byte_off, fc->bit_off, fc->bit_mask);
+}
+
 static void
 mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
 			     const void *item_spec,
@@ -1840,19 +1853,40 @@ mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd,
 	}
 
 	if (m->packet_type & RTE_PTYPE_L4_MASK) {
-		fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];
-		fc->item_idx = item_idx;
-		fc->tag_set = &mlx5dr_definer_ptype_l4_set;
-		fc->tag_mask_set = &mlx5dr_definer_ones_set;
-		DR_CALC_SET(fc, eth_l2, l4_type, false);
+		/*
+		 * Fragmented IP (Internet Protocol) packet type.
+		 * Cannot be combined with Layer 4 Types (TCP/UDP).
+		 * The exact value must be specified in the mask.
+		 */
+		if (m->packet_type == RTE_PTYPE_L4_FRAG) {
+			fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, false)];
+			fc->item_idx = item_idx;
+			fc->tag_set = &mlx5dr_definer_ptype_frag_set;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			DR_CALC_SET(fc, eth_l2, ip_fragmented, false);
+		} else {
+			fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, false)];
+			fc->item_idx = item_idx;
+			fc->tag_set = &mlx5dr_definer_ptype_l4_set;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			DR_CALC_SET(fc, eth_l2, l4_type, false);
+		}
 	}
 
 	if (m->packet_type & RTE_PTYPE_INNER_L4_MASK) {
-		fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];
-		fc->item_idx = item_idx;
-		fc->tag_set = &mlx5dr_definer_ptype_l4_set;
-		fc->tag_mask_set = &mlx5dr_definer_ones_set;
-		DR_CALC_SET(fc, eth_l2, l4_type, true);
+		if (m->packet_type == RTE_PTYPE_INNER_L4_FRAG) {
+			fc = &cd->fc[DR_CALC_FNAME(PTYPE_FRAG, true)];
+			fc->item_idx = item_idx;
+			fc->tag_set = &mlx5dr_definer_ptype_frag_set;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			DR_CALC_SET(fc, eth_l2, ip_fragmented, true);
+		} else {
+			fc = &cd->fc[DR_CALC_FNAME(PTYPE_L4, true)];
+			fc->item_idx = item_idx;
+			fc->tag_set = &mlx5dr_definer_ptype_l4_set;
+			fc->tag_mask_set = &mlx5dr_definer_ones_set;
+			DR_CALC_SET(fc, eth_l2, l4_type, true);
+		}
 	}
 
 	if (m->packet_type & RTE_PTYPE_TUNNEL_MASK) {
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h
index ea07f55d52..791154a7dc 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.h
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h
@@ -148,6 +148,8 @@ enum mlx5dr_definer_fname {
 	MLX5DR_DEFINER_FNAME_PTYPE_L4_O,
 	MLX5DR_DEFINER_FNAME_PTYPE_L4_I,
 	MLX5DR_DEFINER_FNAME_PTYPE_TUNNEL,
+	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_O,
+	MLX5DR_DEFINER_FNAME_PTYPE_FRAG_I,
 	MLX5DR_DEFINER_FNAME_MAX,
 };
 
-- 
2.18.2


  parent reply	other threads:[~2023-10-23 21:12 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-09 16:36 [PATCH 0/5] ptype matching support in mlx5 Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 1/5] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 2/5] net/mlx5/hws: add support for fragmented ptype match Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 3/5] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 4/5] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 5/5] net/mlx5/hws: fix integrity bits level Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 0/7] ptype matching support in mlx5 Alexander Kozyrev
2023-10-23 21:07   ` [PATCH v2 1/7] ethdev: fix ESP packet type description Alexander Kozyrev
2023-10-23 21:07   ` [PATCH v2 2/7] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-23 21:07   ` Alexander Kozyrev [this message]
2023-10-23 21:07   ` [PATCH v2 4/7] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-23 21:07   ` [PATCH v2 5/7] doc: add packet type matching item to release notes Alexander Kozyrev
2023-10-23 21:07   ` [PATCH v2 6/7] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-23 21:07   ` [PATCH v2 7/7] net/mlx5/hws: fix integrity bits level Alexander Kozyrev

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