From: Alexander Kozyrev <akozyrev@nvidia.com>
To: <dev@dpdk.org>
Cc: <orika@nvidia.com>, <matan@nvidia.com>, <michaelba@nvidia.com>,
<valex@nvidia.com>, <suanmingm@nvidia.com>,
<viacheslavo@nvidia.com>
Subject: [PATCH v2 7/7] net/mlx5/hws: fix integrity bits level
Date: Tue, 24 Oct 2023 00:07:07 +0300 [thread overview]
Message-ID: <20231023210707.1344241-8-akozyrev@nvidia.com> (raw)
In-Reply-To: <20231023210707.1344241-1-akozyrev@nvidia.com>
The level field in the integrity item is not taken into account
in the current implementation of hardware steering.
Use this value instead of trying to find out the encapsulation
level according to the protocol items involved.
Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/net/mlx5/hws/mlx5dr_definer.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index c752896ca7..f1f9235956 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -1905,7 +1905,6 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd,
{
const struct rte_flow_item_integrity *m = item->mask;
struct mlx5dr_definer_fc *fc;
- bool inner = cd->tunnel;
if (!m)
return 0;
@@ -1916,7 +1915,7 @@ mlx5dr_definer_conv_item_integrity(struct mlx5dr_definer_conv_data *cd,
}
if (m->l3_ok || m->ipv4_csum_ok || m->l4_ok || m->l4_csum_ok) {
- fc = &cd->fc[DR_CALC_FNAME(INTEGRITY, inner)];
+ fc = &cd->fc[DR_CALC_FNAME(INTEGRITY, m->level)];
fc->item_idx = item_idx;
fc->tag_set = &mlx5dr_definer_integrity_set;
DR_CALC_SET_HDR(fc, oks1, oks1_bits);
@@ -2471,8 +2470,7 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,
break;
case RTE_FLOW_ITEM_TYPE_INTEGRITY:
ret = mlx5dr_definer_conv_item_integrity(&cd, items, i);
- item_flags |= cd.tunnel ? MLX5_FLOW_ITEM_INNER_INTEGRITY :
- MLX5_FLOW_ITEM_OUTER_INTEGRITY;
+ item_flags |= MLX5_FLOW_ITEM_INTEGRITY;
break;
case RTE_FLOW_ITEM_TYPE_CONNTRACK:
ret = mlx5dr_definer_conv_item_conntrack(&cd, items, i);
--
2.18.2
prev parent reply other threads:[~2023-10-23 21:08 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 16:36 [PATCH 0/5] ptype matching support in mlx5 Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 1/5] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 2/5] net/mlx5/hws: add support for fragmented ptype match Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 3/5] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 4/5] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-09 16:36 ` [PATCH 5/5] net/mlx5/hws: fix integrity bits level Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 0/7] ptype matching support in mlx5 Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 1/7] ethdev: fix ESP packet type description Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 2/7] net/mlx5: add support for ptype match in hardware steering Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 3/7] net/mlx5/hws: add support for fragmented ptype match Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 4/7] doc: add PMD ptype item limitations Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 5/7] doc: add packet type matching item to release notes Alexander Kozyrev
2023-10-23 21:07 ` [PATCH v2 6/7] net/mlx5/hws: remove csum check from L3 ok check Alexander Kozyrev
2023-10-23 21:07 ` Alexander Kozyrev [this message]
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