[PATCH v2] event/dlb2: disable PASID for kernel 6.2

[Abdullah Sevincer <abdullah.sevincer@intel.com>]

vfio-pci driver in Linux kernel 6.2 enables PASID by default.
In DLB hardware, enabling PASID puts DLB in SIOV mode. This
breaks DLB PF-PMD mode. For DLB PF-PMD mode to function properly
PASID needs to be disabled for kernel 6.2.

In this commit this issue is addressed and PASID is disabled
by writing a zero to PASID control register.

Signed-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
---
 drivers/event/dlb2/pf/dlb2_main.c | 24 ++++++++++++++++++++++++
 lib/pci/rte_pci.h                 |  4 ++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c
index aa03e4c311..5065c0a9e4 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -190,6 +190,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 	uint16_t rt_ctl_word;
 	uint32_t pri_reqs_dword;
 	uint16_t pri_ctrl_word;
+	uint16_t pasid_ctrl;
 
 	off_t pcie_cap_offset;
 	int pri_cap_offset;
@@ -197,6 +198,7 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 	int err_cap_offset;
 	int acs_cap_offset;
 	int wait_count;
+	int pasid_cap_offset;
 
 	uint16_t devsta_busy_word;
 	uint16_t devctl_word;
@@ -514,6 +516,28 @@ dlb2_pf_reset(struct dlb2_dev *dlb2_dev)
 		}
 	}
 
+	pasid_cap_offset = rte_pci_find_ext_capability(pdev, RTE_PCI_EXT_CAP_ID_PASID);
+
+	if (pasid_cap_offset >= 0) {
+		off = pasid_cap_offset + RTE_PCI_PASID_CTRL;
+
+		if (rte_pci_read_config(pdev, &pasid_ctrl, 2, off) != 2)
+			pasid_ctrl = 0;
+
+		if (pasid_ctrl) {
+
+			DLB2_INFO(dlb2_dev, "DLB2 disabling pasid...\n");
+			pasid_ctrl = 0;
+			ret = rte_pci_write_config(pdev, &pasid_ctrl, 2, off);
+
+			if (ret != 2) {
+				DLB2_LOG_ERR("[%s()] failed to write the pcie config space at offset %d\n",
+						__func__, (int)off);
+				return ret;
+			}
+		}
+	}
+
 	return 0;
 }
 
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
index 69e932d910..d195f01950 100644
--- a/lib/pci/rte_pci.h
+++ b/lib/pci/rte_pci.h
@@ -101,6 +101,10 @@ extern "C" {
 #define RTE_PCI_EXT_CAP_ID_ACS		0x0d	/* Access Control Services */
 #define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV */
 #define RTE_PCI_EXT_CAP_ID_PRI		0x13	/* Page Request Interface */
+#define RTE_PCI_EXT_CAP_ID_PASID        0x1B    /* Process Address Space ID */
+
+/* Process Address Space ID */
+#define RTE_PCI_PASID_CTRL		0x06    /* PASID control register */
 
 /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */
 #define RTE_PCI_ERR_UNCOR_STATUS	0x04	/* Uncorrectable Error Status */
-- 
2.25.1