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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 16:33:04.5805 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b3b59f6-8451-4ce8-821c-08dbd89cb9cc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6441 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Ori Kam Add query for nic flow table support bit. Fixes: 5f44fb1958e5 ("common/mlx5: query capability of registers") Cc: bingz@nvidia.com Signed-off-by: Ori Kam --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index ff2d6d10b7..3afb2e9f80 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1082,6 +1082,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->striding_rq = MLX5_GET(cmd_hca_cap, hcattr, striding_rq); attr->ext_stride_num_range = MLX5_GET(cmd_hca_cap, hcattr, ext_stride_num_range); + attr->nic_flow_table = MLX5_GET(cmd_hca_cap, hcattr, nic_flow_table); attr->max_flow_counter_15_0 = MLX5_GET(cmd_hca_cap, hcattr, max_flow_counter_15_0); attr->max_flow_counter_31_16 = MLX5_GET(cmd_hca_cap, hcattr, -- 2.39.2