From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 7170643238;
Sun, 29 Oct 2023 17:34:07 +0100 (CET)
Received: from mails.dpdk.org (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 4CA8740DCB;
Sun, 29 Oct 2023 17:33:11 +0100 (CET)
Received: from NAM11-CO1-obe.outbound.protection.outlook.com
(mail-co1nam11on2083.outbound.protection.outlook.com [40.107.220.83])
by mails.dpdk.org (Postfix) with ESMTP id 52C7F410FA
for <dev@dpdk.org>; Sun, 29 Oct 2023 17:33:10 +0100 (CET)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
b=Fih7n3yxzY3VVoWISEGC/FEZj9Oxe5D2dq+60qI3kwKCRbXMqWzftKEJm/Yoq3u7macmFr4HXyoAEfsazMy4bqEd2krt7Rhqho7//N/WdieGPWak6vuiksvBr5tf4obrUeBiwF3XrqUqF490LPfCGu03JqxPPaAjDON+gsfu+HPrmdbWpNwL6JF+JhyKlhMUiZXyso0lS9IZszR+8M/LaQ5NZeg5PsBTzfrk0p7wxferPVB+Fhm4w1C8Jqqd0+aHaZFME6S/26rlG/H7x0OQi3izdjuTNctIHpnDACXv+oHOsDOsCAB2tQ61PxgpcYIFoo6jWtq5hqZxpqF4ib0UVA==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector9901;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;
bh=UFAJpmFF1XeKMLNNFjl7x1niU6kyBaGs1qAFZLCrs1w=;
b=kZgdRfqezcfxTvv5sN0SP7mQfBHXQyQKM3JTzF/n1OfgsveRqpFOqH7YPXEOop5nwnWr9xQjiYTUgyvWzqr1QgjjwUExCv6ghikB9Vz9mAiq8JnzM8i/yd1YP9WDR/MU5ePbiH2nCFlxGkJ6U9JQjJWpAnS4KK9HduB0MNgm5OVnkvw05kJkthJFM14fZPZ1+suHBmdFq0iizoCkVGqpnFp0ap65t1RT7sDt+tIULgg3gTBX0wAUPcAhKTMiEifJhpUh0miGOYBg2Bh2q091EpccU9h8hj2+8CZ6/Z7tPYF6abPLB+RHN4nsOnYv66OMESfmIXsJKS60OscVEDCIAA==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
216.228.117.161) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;
dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;
dkim=none (message not signed); arc=none (0)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=UFAJpmFF1XeKMLNNFjl7x1niU6kyBaGs1qAFZLCrs1w=;
b=Rl5517q1gWs68Sb/ip+efsVraKri/+jMxu41aXqHNPCt/x+2NFFzCn0FjxqaJd2xVl/TL7FsuC9mKDf8pF8um6fUXXeKCFNGC5bwuf1H/1uRC+TAO8sklaPzPTQSUs5BvsvNfyH05KRgCYbnrbLifUn+Qky/t3qySaJk2N8q/JpxPn5vI84N/oAfAGjCWjDY90PNfCV7I+4Q/KEssHkMpI4+lP/r0XE+F+iEgzbZhpcnHG6e+pnxrMUYxC66kaKRrKCrbh5cfMR8ZmtuhLy9+0QhsHx/eY0gRzMqGbZaRVRleYOBejufqva9ooct9UONZjF/z4TlOQPlZMzy22wJ2w==
Received: from MN2PR16CA0024.namprd16.prod.outlook.com (2603:10b6:208:134::37)
by DM6PR12MB4388.namprd12.prod.outlook.com (2603:10b6:5:2a9::10) with
Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.27; Sun, 29 Oct
2023 16:33:08 +0000
Received: from BL02EPF0001A0FC.namprd03.prod.outlook.com
(2603:10b6:208:134:cafe::e2) by MN2PR16CA0024.outlook.office365.com
(2603:10b6:208:134::37) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.34 via Frontend
Transport; Sun, 29 Oct 2023 16:33:08 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161)
smtp.mailfrom=nvidia.com;
dkim=none (message not signed)
header.d=none;dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
216.228.117.161 as permitted sender) receiver=protection.outlook.com;
client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C
Received: from mail.nvidia.com (216.228.117.161) by
BL02EPF0001A0FC.mail.protection.outlook.com (10.167.242.103) with Microsoft
SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id
15.20.6933.15 via Frontend Transport; Sun, 29 Oct 2023 16:33:08 +0000
Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com
(10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct
2023 09:32:54 -0700
Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com
(10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 29 Oct
2023 09:32:52 -0700
From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
CC: <getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>, "Ori
Kam" <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko
<viacheslavo@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>
Subject: [PATCH 12/30] net/mlx5: add support for more registers
Date: Sun, 29 Oct 2023 18:31:44 +0200
Message-ID: <20231029163202.216450-12-getelson@nvidia.com>
X-Mailer: git-send-email 2.39.2
In-Reply-To: <20231029163202.216450-1-getelson@nvidia.com>
References: <20231029163202.216450-1-getelson@nvidia.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [10.126.231.35]
X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To
rnnvmail201.nvidia.com (10.129.68.8)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|DM6PR12MB4388:EE_
X-MS-Office365-Filtering-Correlation-Id: 6f4c5cb4-d5bc-436b-a045-08dbd89cbbef
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: Ef4buF0r4687hSE7DZh6F3LanXtfvWlbcbslA0thGpXo189Umvdp6OR3iD0tuQ/omVhWD6fUZVf3A8o1LZ9kxtDK7sY7BoogS9OcqBtYGo+lDfPg/mZKOv7B1G8AvhLE8v3JtUkC/4KYmjdBELQaLhxNPpR+LVxkoIpazzv+z01bQs7RXWBT9EBMcmzbpl3Qn/3skfzpTz6oO8CihbjElgpPWfdwtbjGA+i7Nwga9iIGX0B42EjLY+CG+4ziU7LX1V6xZ+BLIHQRr1bf+PBPRSrFoXY3+nVEcq7JRiOiNX2k/EzjVKc8zvwyRZ97cPAhXgQ5O7pAslHX85uWRlo21aARAHLL+P0228MBmvmU6pRUyYWH/kxaKga47wlJvbDvIvomxA+NtE9suv2u6FLctncPB+Vv9Jze/EWtBDs7/4hQNbBWuWGRCgJWu+Mm+kJ5atw3BhD3mhPZGqvrcEH96HcQkMzatkuBVgINji9PSsfZANQMIjJDC9VAf+LTrsLvtmtHEwJ7//Yn5Gox/9rSwPh1FZINNWZAhMYY0hQxXGrUXkKbZa183yhej0Nf1jp9dhfeoliBivwe5duNJ2I6NPN4rkfncuANFqcqNOlXdVsNOW07zbMym3Wu0pwBNjacEA5waLhUA6riqJtDbFvIQzCwDUc5EiH9lDT0n/WrVk4RE4YfLmT56Vs3O1AIn85ONs0GF1Y9BySn5cOFEsy42fd+f0NzSXeKACVfFlUaCehu/3I+sHIxlrJbqTk2SVkM
X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;
SFS:(13230031)(4636009)(136003)(346002)(376002)(396003)(39860400002)(230922051799003)(82310400011)(1800799009)(186009)(64100799003)(451199024)(36840700001)(40470700004)(46966006)(478600001)(36756003)(86362001)(5660300002)(7696005)(47076005)(40480700001)(6666004)(316002)(6916009)(356005)(7636003)(70206006)(70586007)(54906003)(36860700001)(41300700001)(2906002)(82740400003)(8676002)(8936002)(4326008)(6286002)(16526019)(26005)(336012)(426003)(1076003)(2616005)(107886003)(55016003)(83380400001)(40460700003);
DIR:OUT; SFP:1101;
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2023 16:33:08.0723 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 6f4c5cb4-d5bc-436b-a045-08dbd89cbbef
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];
Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4388
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
From: Ori Kam <orika@nvidia.com>
This commit adds the support for a additional registers that were added
to the HW.
Signed-off-by: Ori Kam <orika@nvidia.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 16 +++++++++----
drivers/common/mlx5/mlx5_devx_cmds.h | 2 +-
drivers/common/mlx5/mlx5_prm.h | 36 ++++++++++++++++++++++++----
drivers/net/mlx5/mlx5.c | 4 ++--
drivers/net/mlx5/mlx5.h | 2 +-
drivers/net/mlx5/mlx5_flow_dv.c | 4 ++++
drivers/net/mlx5/mlx5_flow_hw.c | 2 +-
7 files changed, 53 insertions(+), 13 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 3afb2e9f80..4d8818924a 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -1229,7 +1229,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
attr->modify_outer_ip_ecn = MLX5_GET
(flow_table_nic_cap, hcattr,
ft_header_modify_nic_receive.outer_ip_ecn);
- attr->set_reg_c = 0xff;
+ attr->set_reg_c = 0xffff;
if (attr->nic_flow_table) {
#define GET_RX_REG_X_BITS \
MLX5_GET(flow_table_nic_cap, hcattr, \
@@ -1238,10 +1238,16 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
MLX5_GET(flow_table_nic_cap, hcattr, \
ft_header_modify_nic_transmit.metadata_reg_c_x)
- uint32_t tx_reg, rx_reg;
+ uint32_t tx_reg, rx_reg, reg_c_8_15;
tx_reg = GET_TX_REG_X_BITS;
+ reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_transmit.metadata_reg_c_8_15);
+ tx_reg |= ((0xff & reg_c_8_15) << 8);
rx_reg = GET_RX_REG_X_BITS;
+ reg_c_8_15 = MLX5_GET(flow_table_nic_cap, hcattr,
+ ft_field_support_2_nic_receive.metadata_reg_c_8_15);
+ rx_reg |= ((0xff & reg_c_8_15) << 8);
attr->set_reg_c &= (rx_reg & tx_reg);
#undef GET_RX_REG_X_BITS
@@ -1371,7 +1377,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
MLX5_GET(esw_cap, hcattr, esw_manager_vport_number);
}
if (attr->eswitch_manager) {
- uint32_t esw_reg;
+ uint32_t esw_reg, reg_c_8_15;
hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc,
MLX5_GET_HCA_CAP_OP_MOD_ESW_FLOW_TABLE |
@@ -1380,7 +1386,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
return rc;
esw_reg = MLX5_GET(flow_table_esw_cap, hcattr,
ft_header_modify_esw_fdb.metadata_reg_c_x);
- attr->set_reg_c &= esw_reg;
+ reg_c_8_15 = MLX5_GET(flow_table_esw_cap, hcattr,
+ ft_field_support_2_esw_fdb.metadata_reg_c_8_15);
+ attr->set_reg_c &= ((0xff & reg_c_8_15) << 8) | esw_reg;
}
return 0;
error:
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 11772431ae..7f23e925a5 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -301,7 +301,7 @@ struct mlx5_hca_attr {
uint32_t cqe_compression_128:1;
uint32_t multi_pkt_send_wqe:1;
uint32_t enhanced_multi_pkt_send_wqe:1;
- uint32_t set_reg_c:8;
+ uint32_t set_reg_c:16;
uint32_t nic_flow_table:1;
uint32_t modify_outer_ip_ecn:1;
union {
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 19c6d0282b..2b499666f8 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -840,6 +840,14 @@ enum mlx5_modification_field {
MLX5_MODI_IN_MPLS_LABEL_3,
MLX5_MODI_IN_MPLS_LABEL_4,
MLX5_MODI_OUT_IPV6_NEXT_HDR = 0x4A,
+ MLX5_MODI_META_REG_C_8 = 0x8F,
+ MLX5_MODI_META_REG_C_9 = 0x90,
+ MLX5_MODI_META_REG_C_10 = 0x91,
+ MLX5_MODI_META_REG_C_11 = 0x92,
+ MLX5_MODI_META_REG_C_12 = 0x93,
+ MLX5_MODI_META_REG_C_13 = 0x94,
+ MLX5_MODI_META_REG_C_14 = 0x95,
+ MLX5_MODI_META_REG_C_15 = 0x96,
MLX5_MODI_INVALID = INT_MAX,
};
@@ -2227,8 +2235,22 @@ struct mlx5_ifc_ft_fields_support_2_bits {
u8 inner_ipv4_checksum_ok[0x1];
u8 inner_l4_checksum_ok[0x1];
u8 outer_ipv4_checksum_ok[0x1];
- u8 outer_l4_checksum_ok[0x1];
- u8 reserved_at_20[0x60];
+ u8 outer_l4_checksum_ok[0x1]; /* end of DW0 */
+ u8 reserved_at_20[0x18];
+ union {
+ struct {
+ u8 metadata_reg_c_15[0x1];
+ u8 metadata_reg_c_14[0x1];
+ u8 metadata_reg_c_13[0x1];
+ u8 metadata_reg_c_12[0x1];
+ u8 metadata_reg_c_11[0x1];
+ u8 metadata_reg_c_10[0x1];
+ u8 metadata_reg_c_9[0x1];
+ u8 metadata_reg_c_8[0x1];
+ };
+ u8 metadata_reg_c_8_15[0x8];
+ }; /* end of DW1 */
+ u8 reserved_at_40[0x40];
};
struct mlx5_ifc_flow_table_nic_cap_bits {
@@ -2250,7 +2272,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
ft_header_modify_nic_receive;
struct mlx5_ifc_ft_fields_support_2_bits
ft_field_support_2_nic_receive;
- u8 reserved_at_1480[0x780];
+ u8 reserved_at_1480[0x280];
+ struct mlx5_ifc_ft_fields_support_2_bits
+ ft_field_support_2_nic_transmit;
+ u8 reserved_at_1780[0x480];
struct mlx5_ifc_ft_fields_support_bits
ft_header_modify_nic_transmit;
u8 reserved_at_2000[0x6000];
@@ -2259,7 +2284,10 @@ struct mlx5_ifc_flow_table_nic_cap_bits {
struct mlx5_ifc_flow_table_esw_cap_bits {
u8 reserved_at_0[0x800];
struct mlx5_ifc_ft_fields_support_bits ft_header_modify_esw_fdb;
- u8 reserved_at_C00[0x7400];
+ u8 reserved_at_C00[0x800];
+ struct mlx5_ifc_ft_fields_support_2_bits
+ ft_field_support_2_esw_fdb;
+ u8 reserved_at_1480[0x6b80];
};
enum mlx5_ifc_cross_vhca_object_to_object_supported_types {
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 840c566162..cdb4eeb612 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1604,8 +1604,8 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
{
struct mlx5_dev_registers *reg = &sh->registers;
uint32_t meta_mode = sh->config.dv_xmeta_en;
- uint8_t masks = (uint8_t)sh->cdev->config.hca_attr.set_reg_c;
- uint8_t unset = 0;
+ uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;
+ uint16_t unset = 0;
uint32_t i, j;
/*
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index a0dcd788b4..0289cbd04b 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1373,7 +1373,7 @@ struct mlx5_hws_cnt_svc_mng {
struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned;
};
-#define MLX5_FLOW_HW_TAGS_MAX 8
+#define MLX5_FLOW_HW_TAGS_MAX 12
struct mlx5_dev_registers {
enum modify_reg aso_reg;
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 9268a07c84..bdc8d0076a 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -970,6 +970,10 @@ static enum mlx5_modification_field reg_to_field[] = {
[REG_C_5] = MLX5_MODI_META_REG_C_5,
[REG_C_6] = MLX5_MODI_META_REG_C_6,
[REG_C_7] = MLX5_MODI_META_REG_C_7,
+ [REG_C_8] = MLX5_MODI_META_REG_C_8,
+ [REG_C_9] = MLX5_MODI_META_REG_C_9,
+ [REG_C_10] = MLX5_MODI_META_REG_C_10,
+ [REG_C_11] = MLX5_MODI_META_REG_C_11,
};
/**
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 9e549a1ba2..ceeb82a649 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -5615,7 +5615,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,
{
const struct rte_flow_item_tag *tag =
(const struct rte_flow_item_tag *)items[i].spec;
- uint8_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
+ uint16_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
if (!((1 << (tag->index - REG_C_0)) & regcs))
return rte_flow_error_set(error, EINVAL,
--
2.39.2