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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000FCC1.mail.protection.outlook.com (10.167.242.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.19 via Frontend Transport; Wed, 1 Nov 2023 04:44:55 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 21:44:43 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 31 Oct 2023 21:44:40 -0700 From: Rongwei Liu To: , , , , , CC: Alex Vesker , Erez Shitrit Subject: [PATCH v4 03/13] net/mlx5/hws: allow jump to TIR over FDB Date: Wed, 1 Nov 2023 06:44:09 +0200 Message-ID: <20231101044419.732726-4-rongweil@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20231101044419.732726-1-rongweil@nvidia.com> References: <20231031105131.441078-1-rongweil@nvidia.com> <20231101044419.732726-1-rongweil@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC1:EE_|IA1PR12MB6139:EE_ X-MS-Office365-Filtering-Correlation-Id: bd92ba3e-803a-49d4-533c-08dbda954b68 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2023 04:44:55.1761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bd92ba3e-803a-49d4-533c-08dbda954b68 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6139 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Alex Vesker Current TIR action is allowed to be used only for NIC RX, this will allow TIR action over FDB for RX traffic in case of TX traffic packets will be dropped. Signed-off-by: Alex Vesker Reviewed-by: Erez Shitrit Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_prm.h | 2 ++ drivers/net/mlx5/hws/mlx5dr_action.c | 17 ++++++++++++++++- drivers/net/mlx5/hws/mlx5dr_cmd.c | 4 ++++ drivers/net/mlx5/hws/mlx5dr_cmd.h | 1 + 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 2b499666f8..5259031a04 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -2418,6 +2418,8 @@ struct mlx5_ifc_wqe_based_flow_table_cap_bits { u8 reserved_at_180[0x10]; u8 ste_format_gen_wqe[0x10]; u8 linear_match_definer_reg_c3[0x20]; + u8 fdb_jump_to_tir_stc[0x1]; + u8 reserved_at_1c1[0x1f]; }; union mlx5_ifc_hca_cap_union_bits { diff --git a/drivers/net/mlx5/hws/mlx5dr_action.c b/drivers/net/mlx5/hws/mlx5dr_action.c index f794d6cd78..1bace23c58 100644 --- a/drivers/net/mlx5/hws/mlx5dr_action.c +++ b/drivers/net/mlx5/hws/mlx5dr_action.c @@ -389,7 +389,15 @@ mlx5dr_action_fixup_stc_attr(struct mlx5dr_context *ctx, } use_fixup = true; break; - + case MLX5_IFC_STC_ACTION_TYPE_JUMP_TO_TIR: + /* TIR is allowed on RX side, requires mask in case of FDB */ + if (fw_tbl_type == FS_FT_FDB_TX) { + fixup_stc_attr->action_type = MLX5_IFC_STC_ACTION_TYPE_DROP; + fixup_stc_attr->action_offset = MLX5DR_ACTION_OFFSET_HIT; + fixup_stc_attr->stc_offset = stc_attr->stc_offset; + use_fixup = true; + } + break; default: break; } @@ -859,6 +867,13 @@ mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx, return NULL; } + if ((flags & MLX5DR_ACTION_FLAG_ROOT_FDB) || + (flags & MLX5DR_ACTION_FLAG_HWS_FDB && !ctx->caps->fdb_tir_stc)) { + DR_LOG(ERR, "TIR action not support on FDB"); + rte_errno = ENOTSUP; + return NULL; + } + if (!is_local) { DR_LOG(ERR, "TIR should be created on local ibv_device, flags: 0x%x", flags); diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.c b/drivers/net/mlx5/hws/mlx5dr_cmd.c index f24651041c..a07378bc42 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.c +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.c @@ -1259,6 +1259,10 @@ int mlx5dr_cmd_query_caps(struct ibv_context *ctx, caps->supp_ste_format_gen_wqe = MLX5_GET(query_hca_cap_out, out, capability.wqe_based_flow_table_cap. ste_format_gen_wqe); + + caps->fdb_tir_stc = MLX5_GET(query_hca_cap_out, out, + capability.wqe_based_flow_table_cap. + fdb_jump_to_tir_stc); } if (caps->eswitch_manager) { diff --git a/drivers/net/mlx5/hws/mlx5dr_cmd.h b/drivers/net/mlx5/hws/mlx5dr_cmd.h index 03db62e2e2..2b44f0e1f2 100644 --- a/drivers/net/mlx5/hws/mlx5dr_cmd.h +++ b/drivers/net/mlx5/hws/mlx5dr_cmd.h @@ -236,6 +236,7 @@ struct mlx5dr_cmd_query_caps { uint8_t log_header_modify_argument_granularity; uint8_t log_header_modify_argument_max_alloc; uint8_t sq_ts_format; + uint8_t fdb_tir_stc; uint64_t definer_format_sup; uint32_t trivial_match_definer; uint32_t vhca_id; -- 2.27.0