From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B360B4327C; Fri, 3 Nov 2023 19:29:45 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6706542D72; Fri, 3 Nov 2023 19:29:40 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id 8B2004029E for ; Fri, 3 Nov 2023 19:29:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699036178; x=1730572178; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AfTkygmDupahS5+ygcpOUWqDHNN4y8b5gBbaCr8Hekg=; b=JNlc/Swq4VvgswphA7lricI0YcANprHcbtB5Zk0NadMwyCs6jWVenMtD vX4nQq3/NoUeYfM5chWyISAPmkoexjoNdTlaRQLrdGTboYVzoLElDCywp jwAu2Z2N/PPdCwQs2K1lpArCpMXW1eTyAe673pzh+ze5J9AAN1ZbQ8sl+ dOLTw04NIzxgrXLUB1kzs36zXNRp7jDa6X5cGr00I+BknYb1iQoymvDW7 NO9JYXh1QpmDYS0w6k/HhbP0BOgsIOVt2jCvx+zn7c0zyWrqCKUtnGsKx AQpBvkjSpJC/RZK4mvjeumysuOZ8YUo9vCf6cTgQKm7ZQFxoPISMcjZfQ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10883"; a="391867083" X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="391867083" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2023 11:29:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,273,1694761200"; d="scan'208";a="9465875" Received: from txanpdk02.an.intel.com ([10.123.117.76]) by orviesa001.jf.intel.com with ESMTP; 03 Nov 2023 11:29:38 -0700 From: Abdullah Sevincer To: dev@dpdk.org Cc: jerinj@marvell.com, mike.ximing.chen@intel.com, bruce.richardson@intel.com, thomas@monjalon.net, Abdullah Sevincer Subject: [PATCH v6 1/2] bus/pci: add function to enable/disable PASID Date: Fri, 3 Nov 2023 13:29:32 -0500 Message-Id: <20231103182933.2831662-2-abdullah.sevincer@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231103182933.2831662-1-abdullah.sevincer@intel.com> References: <20231103182933.2831662-1-abdullah.sevincer@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org This commit implements an internal api to enable and disable PASID for a device e.g. device driver event/dlb2. For kernels when PASID enabled by default it breaks DLB functionality, hence disabling PASID is required for DLB to function properly. PASID capability is not exposed to users hence offset can not be retrieved by rte_pci_find_ext_capability() api. Therefore, api implemented in this commit accepts an offset for PASID with an enable flag which is used to enable/disable PASID. Signed-off-by: Abdullah Sevincer --- drivers/bus/pci/pci_common.c | 7 +++++++ drivers/bus/pci/rte_bus_pci.h | 13 +++++++++++++ drivers/bus/pci/version.map | 1 + lib/pci/rte_pci.h | 4 ++++ 4 files changed, 25 insertions(+) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index 921d957bf6..5aac2406f1 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -938,6 +938,13 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable) return 0; } +int +rte_pci_pasid_ena_dis(const struct rte_pci_device *dev, off_t offset, bool enable) +{ + uint16_t pasid = enable; + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 ? -1 : 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 21e234abf0..d45b7bf2ab 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -295,6 +295,19 @@ void rte_pci_ioport_read(struct rte_pci_ioport *p, void rte_pci_ioport_write(struct rte_pci_ioport *p, const void *data, size_t len, off_t offset); +/** + * Enable/Disable PASID. + * + * @param dev + * A pointer to a rte_pci_device structure. + * @param offset + * Offset of the PASID external capability. + * @param enable + * Flag to enable or disable PASID. + */ +__rte_internal +int rte_pci_pasid_ena_dis(const struct rte_pci_device *dev, off_t offset, bool enable); + #ifdef __cplusplus } #endif diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map index 74c5b075d5..01e6a09eb6 100644 --- a/drivers/bus/pci/version.map +++ b/drivers/bus/pci/version.map @@ -36,6 +36,7 @@ INTERNAL { global: rte_pci_get_sysfs_path; + rte_pci_pasid_ena_dis; rte_pci_register; rte_pci_unregister; }; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index 69e932d910..d195f01950 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -101,6 +101,10 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ + +/* Process Address Space ID */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ -- 2.25.1