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From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>,
	"Kiran Kumar K" <kirankumark@marvell.com>,
	Sunil Kumar Kori <skori@marvell.com>,
	Satha Rao <skoteshwar@marvell.com>
Cc: <dev@dpdk.org>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Subject: [PATCH v2 2/3] common/cnxk: update scheduler base code
Date: Mon, 11 Dec 2023 18:53:19 +0530	[thread overview]
Message-ID: <20231211132320.1254-2-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20231211132320.1254-1-pbhagavatula@marvell.com>

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Update event scheduler base code.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/common/cnxk/hw/ssow.h |  4 ++++
 drivers/common/cnxk/roc_sso.c | 34 +++++++++++++++++++++++-----------
 drivers/common/cnxk/roc_sso.h |  2 +-
 3 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/drivers/common/cnxk/hw/ssow.h b/drivers/common/cnxk/hw/ssow.h
index 618ab7973b..c146a8c3ef 100644
--- a/drivers/common/cnxk/hw/ssow.h
+++ b/drivers/common/cnxk/hw/ssow.h
@@ -54,6 +54,8 @@
 #define SSOW_LF_GWS_OP_SWTAG_FULL1   (0xc28ull)
 #define SSOW_LF_GWS_OP_GWC_INVAL     (0xe00ull)
 
+#define SSOW_LF_GWS_MAX_NW_TIM_US (0x400) /* [CN9K, CN10K) */
+
 /* Enum offsets */
 
 #define SSOW_LF_INT_VEC_IOP (0x0ull)
@@ -65,6 +67,8 @@
 #define SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT 63
 #define SSOW_LF_GWS_TAG_PEND_SWITCH_BIT	  62
 #define SSOW_LF_GWS_TAG_PEND_DESCHED_BIT  58
+#define SSOW_LF_GWS_TAG_PEND_FLUSH	  56
+#define SSOW_LF_GWS_TAG_PEND_SWUNT	  54
 #define SSOW_LF_GWS_TAG_HEAD_BIT	  35
 
 #endif /* __SSOW_HW_H__ */
diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c
index f09b535c80..e5c16b2a05 100644
--- a/drivers/common/cnxk/roc_sso.c
+++ b/drivers/common/cnxk/roc_sso.c
@@ -17,6 +17,11 @@ sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,
 	struct mbox *mbox = mbox_get(dev->mbox);
 	int rc = -ENOSPC;
 
+	if (!nb_lf) {
+		mbox_put(mbox);
+		return 0;
+	}
+
 	switch (lf_type) {
 	case SSO_LF_TYPE_HWS: {
 		struct ssow_lf_alloc_req *req;
@@ -56,6 +61,11 @@ sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf)
 	struct mbox *mbox = mbox_get(dev->mbox);
 	int rc = -ENOSPC;
 
+	if (!nb_lf) {
+		mbox_put(mbox);
+		return 0;
+	}
+
 	switch (lf_type) {
 	case SSO_LF_TYPE_HWS: {
 		struct ssow_lf_free_req *req;
@@ -98,6 +108,11 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type,
 	struct rsrc_attach_req *req;
 	int rc = -ENOSPC;
 
+	if (!nb_lf) {
+		mbox_put(mbox);
+		return 0;
+	}
+
 	req = mbox_alloc_msg_attach_resources(mbox);
 	if (req == NULL)
 		goto exit;
@@ -264,13 +279,10 @@ roc_sso_hwgrp_base_get(struct roc_sso *roc_sso, uint16_t hwgrp)
 }
 
 uint64_t
-roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns)
+roc_sso_ns_to_gw(uint64_t base, uint64_t ns)
 {
-	struct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;
-	uint64_t current_us, current_ns, new_ns;
-	uintptr_t base;
+	uint64_t current_us;
 
-	base = dev->bar2 + (RVU_BLOCK_ADDR_SSOW << 20);
 	current_us = plt_read64(base + SSOW_LF_GWS_NW_TIM);
 	/* From HRM, table 14-19:
 	 * The SSOW_LF_GWS_NW_TIM[NW_TIM] period is specified in n-1 notation.
@@ -279,14 +291,11 @@ roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns)
 
 	/* From HRM, table 14-1:
 	 * SSOW_LF_GWS_NW_TIM[NW_TIM] specifies the minimum timeout. The SSO
-	 * hardware times out a GET_WORK request within 2 usec of the minimum
+	 * hardware times out a GET_WORK request within 1 usec of the minimum
 	 * timeout specified by SSOW_LF_GWS_NW_TIM[NW_TIM].
 	 */
-	current_us += 2;
-	current_ns = current_us * 1E3;
-	new_ns = (ns - PLT_MIN(ns, current_ns));
-	new_ns = !new_ns ? 1 : new_ns;
-	return (new_ns * plt_tsc_hz()) / 1E9;
+	current_us += 1;
+	return PLT_MAX(1UL, (uint64_t)PLT_DIV_CEIL(ns, (current_us * 1E3)));
 }
 
 int
@@ -705,6 +714,9 @@ roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)
 	struct dev *dev = &sso->dev;
 	int rc;
 
+	if (!hwgrps)
+		return 0;
+
 	rc = sso_hwgrp_release_xaq(dev, hwgrps);
 	return rc;
 }
diff --git a/drivers/common/cnxk/roc_sso.h b/drivers/common/cnxk/roc_sso.h
index 64f14b8119..26061f25f8 100644
--- a/drivers/common/cnxk/roc_sso.h
+++ b/drivers/common/cnxk/roc_sso.h
@@ -83,7 +83,7 @@ int __roc_api roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso,
 int __roc_api roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso,
 					 uint16_t hwgrp, uint8_t weight,
 					 uint8_t affinity, uint8_t priority);
-uint64_t __roc_api roc_sso_ns_to_gw(struct roc_sso *roc_sso, uint64_t ns);
+uint64_t __roc_api roc_sso_ns_to_gw(uint64_t base, uint64_t ns);
 int __roc_api roc_sso_hws_link(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],
 			       uint16_t nb_hwgrp, uint8_t set);
 int __roc_api roc_sso_hws_unlink(struct roc_sso *roc_sso, uint8_t hws, uint16_t hwgrp[],
-- 
2.25.1


  reply	other threads:[~2023-12-11 13:23 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-07  6:56 [PATCH] event/cnxk: update " pbhagavatula
2023-12-11 12:00 ` Jerin Jacob
2023-12-11 13:23 ` [PATCH v2 1/3] common/cnxk: update timer " pbhagavatula
2023-12-11 13:23   ` pbhagavatula [this message]
2023-12-11 13:23   ` [PATCH v2 3/3] event/cnxk: add option to update links via mbox pbhagavatula
2023-12-12  5:03     ` Jerin Jacob

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