From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F979432AF; Fri, 5 Jan 2024 22:19:07 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2399F4068A; Fri, 5 Jan 2024 22:18:53 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by mails.dpdk.org (Postfix) with ESMTP id 64D94402E5 for ; Fri, 5 Jan 2024 22:18:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1704489530; x=1736025530; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MK24dHu21RlWQM/fMSxifXBBpCOVlXtfO7TsF5KSyVg=; b=WTikOilMv2y6uUzrvzxnd4lATzNUT/zAd7LSktHuEuy0X+7m4YwIMPx0 u/Aj7x4eSGc2GHqSwK+EMZzCjsdXdXik+OwEomiwKSrQDWzBQvpghZRTZ KHaljxyfREvYxafg+lmdTN02oxLGKYIDWzWmiJGW5V0LzvrQiA7i9efPi UC+00JTU4xYXo7zb+xTZX6xU8YLOkXVAA85ZzRiuCJ/ltX2BAeYmKOnD4 +jeZRfsHptKbTfeAGvYQfLNsQNL93dZXtXxjAWdLhZcjhMXlnxUyVcsDj PGDfM0/7g+jtUHINAch4kUhS35zauEaQ85FFkEPLiMY0/rQ+KP65D+0sp A==; X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="377738608" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="377738608" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jan 2024 13:18:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10944"; a="784302120" X-IronPort-AV: E=Sophos;i="6.04,334,1695711600"; d="scan'208";a="784302120" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmsmga007.fm.intel.com with ESMTP; 05 Jan 2024 13:18:48 -0800 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas Subject: [PATCH v4 2/4] baseband/fpga_5gnr_fec: add Vista Creek variant Date: Fri, 5 Jan 2024 13:15:17 -0800 Message-Id: <20240105211519.185086-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240105211519.185086-1-hernan.vargas@intel.com> References: <20240105211519.185086-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Create a new file vc_5gnr_pmd.h to store structures and macros specific to Vista Creek 5G FPGA implementation and rename functions specific to the Vista Creek variant. Signed-off-by: Hernan Vargas --- .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h | 183 ++----- .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c | 475 +++++++++--------- drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h | 140 ++++++ 3 files changed, 398 insertions(+), 400 deletions(-) create mode 100644 drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h diff --git a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h index 9300349a731b..982e956dc819 100644 --- a/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h +++ b/drivers/baseband/fpga_5gnr_fec/fpga_5gnr_fec.h @@ -8,6 +8,8 @@ #include #include +#include "vc_5gnr_pmd.h" + /* Helper macro for logging */ #define rte_bbdev_log(level, fmt, ...) \ rte_log(RTE_LOG_ ## level, fpga_5gnr_fec_logtype, fmt "\n", \ @@ -25,32 +27,20 @@ #define FPGA_5GNR_FEC_PF_DRIVER_NAME intel_fpga_5gnr_fec_pf #define FPGA_5GNR_FEC_VF_DRIVER_NAME intel_fpga_5gnr_fec_vf -/* FPGA 5GNR FEC PCI vendor & device IDs */ -#define FPGA_5GNR_FEC_VENDOR_ID (0x8086) -#define FPGA_5GNR_FEC_PF_DEVICE_ID (0x0D8F) -#define FPGA_5GNR_FEC_VF_DEVICE_ID (0x0D90) - -/* Align DMA descriptors to 256 bytes - cache-aligned */ -#define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8) -/* Ring size is in 256 bits (32 bytes) units */ -#define FPGA_RING_DESC_LEN_UNIT_BYTES (32) -/* Maximum size of queue */ -#define FPGA_5GNR_RING_MAX_SIZE (1024) - -#define FPGA_NUM_UL_QUEUES (32) -#define FPGA_NUM_DL_QUEUES (32) -#define FPGA_TOTAL_NUM_QUEUES (FPGA_NUM_UL_QUEUES + FPGA_NUM_DL_QUEUES) -#define FPGA_NUM_INTR_VEC (FPGA_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET) - #define FPGA_5GNR_INVALID_HW_QUEUE_ID (0xFFFFFFFF) - #define FPGA_5GNR_QUEUE_FLUSH_TIMEOUT_US (1000) #define FPGA_5GNR_HARQ_RDY_TIMEOUT (10) #define FPGA_5GNR_TIMEOUT_CHECK_INTERVAL (5) #define FPGA_5GNR_DDR_OVERFLOW (0x10) - #define FPGA_5GNR_DDR_WR_DATA_LEN_IN_BYTES 8 #define FPGA_5GNR_DDR_RD_DATA_LEN_IN_BYTES 8 +/* Align DMA descriptors to 256 bytes - cache-aligned. */ +#define FPGA_5GNR_RING_DESC_ENTRY_LENGTH (8) +/* Maximum size of queue. */ +#define FPGA_5GNR_RING_MAX_SIZE (1024) + +#define VC_5GNR_FPGA_VARIANT 0 +#define AGX100_FPGA_VARIANT 1 /* Constants from K0 computation from 3GPP 38.212 Table 5.4.2.1-2 */ #define N_ZC_1 66 /* N = 66 Zc for BG 1 */ @@ -62,32 +52,7 @@ #define K0_3_1 56 /* K0 fraction numerator for rv 3 and BG 1 */ #define K0_3_2 43 /* K0 fraction numerator for rv 3 and BG 2 */ -/* FPGA 5GNR FEC Register mapping on BAR0 */ -enum { - FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /* len: 4B */ - FPGA_5GNR_FEC_CONFIGURATION = 0x00000004, /* len: 2B */ - FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /* len: 1B */ - FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000a, /* len: 2B */ - FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000c, /* len: 2B */ - FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /* len: 4B */ - FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001c, /* len: 4B */ - FPGA_5GNR_FEC_QUEUE_MAP = 0x00000040, /* len: 256B */ - FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /* len: 2048B */ - FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /* len: 4B */ - FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /* len: 8B */ - FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /* len: 1B */ - FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /* len: 4B */ - FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /* len: 1B */ - FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /* len: 1B */ - FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /* len: 8B */ - FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /* len: 1B */ - FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /* len: 1B */ - FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /* len: 4B */ - FPGA_5GNR_FEC_MUTEX = 0x00000A60, /* len: 4B */ - FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /* len: 4B */ -}; - -/* FPGA 5GNR FEC Ring Control Registers */ +/* FPGA 5GNR Ring Control Registers. */ enum { FPGA_5GNR_FEC_RING_HEAD_ADDR = 0x00000008, FPGA_5GNR_FEC_RING_SIZE = 0x00000010, @@ -98,113 +63,27 @@ enum { FPGA_5GNR_FEC_RING_HEAD_POINT = 0x0000001C }; -/* FPGA 5GNR FEC DESCRIPTOR ERROR */ +/* VC 5GNR and AGX100 common register mapping on BAR0. */ enum { - DESC_ERR_NO_ERR = 0x0, - DESC_ERR_K_P_OUT_OF_RANGE = 0x1, - DESC_ERR_Z_C_NOT_LEGAL = 0x2, - DESC_ERR_DESC_OFFSET_ERR = 0x3, - DESC_ERR_DESC_READ_FAIL = 0x8, - DESC_ERR_DESC_READ_TIMEOUT = 0x9, - DESC_ERR_DESC_READ_TLP_POISONED = 0xA, - DESC_ERR_HARQ_INPUT_LEN = 0xB, - DESC_ERR_CB_READ_FAIL = 0xC, - DESC_ERR_CB_READ_TIMEOUT = 0xD, - DESC_ERR_CB_READ_TLP_POISONED = 0xE, - DESC_ERR_HBSTORE_ERR = 0xF -}; - - -/* FPGA 5GNR FEC DMA Encoding Request Descriptor */ -struct __rte_packed fpga_dma_enc_desc { - uint32_t done:1, - rsrvd0:7, - error:4, - rsrvd1:4, - num_null:10, - rsrvd2:6; - uint32_t ncb:15, - rsrvd3:1, - k0:16; - uint32_t irq_en:1, - crc_en:1, - rsrvd4:1, - qm_idx:3, - bg_idx:1, - zc:9, - desc_idx:10, - rsrvd5:6; - uint16_t rm_e; - uint16_t k_; - uint32_t out_addr_lw; - uint32_t out_addr_hi; - uint32_t in_addr_lw; - uint32_t in_addr_hi; - - union { - struct { - /* Virtual addresses used to retrieve SW context info */ - void *op_addr; - /* Stores information about total number of Code Blocks - * in currently processed Transport Block - */ - uint64_t cbs_in_op; - }; - - uint8_t sw_ctxt[FPGA_RING_DESC_LEN_UNIT_BYTES * - (FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; - }; -}; - - -/* FPGA 5GNR DPC FEC DMA Decoding Request Descriptor */ -struct __rte_packed fpga_dma_dec_desc { - uint32_t done:1, - iter:5, - et_pass:1, - crcb_pass:1, - error:4, - qm_idx:3, - max_iter:5, - bg_idx:1, - rsrvd0:1, - harqin_en:1, - zc:9; - uint32_t hbstroe_offset:22, - num_null:10; - uint32_t irq_en:1, - ncb:15, - desc_idx:10, - drop_crc24b:1, - crc24b_ind:1, - rv:2, - et_dis:1, - rsrvd2:1; - uint32_t harq_input_length:16, - rm_e:16;/*the inbound data byte length*/ - uint32_t out_addr_lw; - uint32_t out_addr_hi; - uint32_t in_addr_lw; - uint32_t in_addr_hi; - - union { - struct { - /* Virtual addresses used to retrieve SW context info */ - void *op_addr; - /* Stores information about total number of Code Blocks - * in currently processed Transport Block - */ - uint8_t cbs_in_op; - }; - - uint32_t sw_ctxt[8 * (FPGA_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; - }; -}; - -/* FPGA 5GNR DMA Descriptor */ -union fpga_dma_desc { - struct fpga_dma_enc_desc enc_req; - struct fpga_dma_dec_desc dec_req; + FPGA_5GNR_FEC_VERSION_ID = 0x00000000, /**< len: 4B. */ + FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE = 0x00000008, /**< len: 1B. */ + FPGA_5GNR_FEC_LOAD_BALANCE_FACTOR = 0x0000000A, /**< len: 2B. */ + FPGA_5GNR_FEC_RING_DESC_LEN = 0x0000000C, /**< len: 2B. */ + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_LW = 0x00000018, /**< len: 4B. */ + FPGA_5GNR_FEC_VFQ_FLUSH_STATUS_HI = 0x0000001C, /**< len: 4B. */ + FPGA_5GNR_FEC_RING_CTRL_REGS = 0x00000200, /**< len: 2048B. */ + FPGA_5GNR_FEC_DDR4_WR_ADDR_REGS = 0x00000A00, /**< len: 4B. */ + FPGA_5GNR_FEC_DDR4_WR_DATA_REGS = 0x00000A08, /**< len: 8B. */ + FPGA_5GNR_FEC_DDR4_WR_DONE_REGS = 0x00000A10, /**< len: 1B. */ + FPGA_5GNR_FEC_DDR4_RD_ADDR_REGS = 0x00000A18, /**< len: 4B. */ + FPGA_5GNR_FEC_DDR4_RD_DONE_REGS = 0x00000A20, /**< len: 1B. */ + FPGA_5GNR_FEC_DDR4_RD_RDY_REGS = 0x00000A28, /**< len: 1B. */ + FPGA_5GNR_FEC_DDR4_RD_DATA_REGS = 0x00000A30, /**< len: 8B. */ + FPGA_5GNR_FEC_DDR4_ADDR_RDY_REGS = 0x00000A38, /**< len: 1B. */ + FPGA_5GNR_FEC_HARQ_BUF_SIZE_RDY_REGS = 0x00000A40, /**< len: 1B. */ + FPGA_5GNR_FEC_HARQ_BUF_SIZE_REGS = 0x00000A48, /**< len: 4B. */ + FPGA_5GNR_FEC_MUTEX = 0x00000A60, /**< len: 4B. */ + FPGA_5GNR_FEC_MUTEX_RESET = 0x00000A68 /**< len: 4B. */ }; /* FPGA 5GNR Ring Control Register. */ @@ -257,7 +136,7 @@ struct fpga_5gnr_fec_device { /** Structure associated with each queue. */ struct __rte_cache_aligned fpga_5gnr_queue { struct fpga_5gnr_ring_ctrl_reg ring_ctrl_reg; /**< Ring Control Register */ - union fpga_dma_desc *ring_addr; /* Virtual address of software ring */ + union vc_5gnr_dma_desc *vc_5gnr_ring_addr; /**< Virtual address of VC 5GNR software ring. */ uint64_t *ring_head_addr; /* Virtual address of completion_head */ uint64_t shadow_completion_head; /* Shadow completion head value */ uint16_t head_free_desc; /* Ring head */ diff --git a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c index 5fbe913ddbe2..f9a776e6aea5 100644 --- a/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c +++ b/drivers/baseband/fpga_5gnr_fec/rte_fpga_5gnr_fec.c @@ -69,12 +69,11 @@ print_ring_reg_debug_info(void *mmio_base, uint32_t offset) FPGA_5GNR_FEC_RING_HEAD_POINT)); } -/* Read Static Register of FPGA 5GNR FEC device */ +/* Read Static Register of Vista Creek device. */ static inline void print_static_reg_debug_info(void *mmio_base) { - uint16_t config = fpga_5gnr_reg_read_16(mmio_base, - FPGA_5GNR_FEC_CONFIGURATION); + uint16_t config = fpga_5gnr_reg_read_16(mmio_base, VC_5GNR_CONFIGURATION); uint8_t qmap_done = fpga_5gnr_reg_read_8(mmio_base, FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE); uint16_t lb_factor = fpga_5gnr_reg_read_16(mmio_base, @@ -89,53 +88,53 @@ print_static_reg_debug_info(void *mmio_base) rte_bbdev_log_debug("Queue-PF/VF Mapping Table = %s", (qmap_done > 0) ? "READY" : "NOT-READY"); rte_bbdev_log_debug("Ring Descriptor Size = %u bytes", - ring_desc_len*FPGA_RING_DESC_LEN_UNIT_BYTES); + ring_desc_len*VC_5GNR_RING_DESC_LEN_UNIT_BYTES); } -/* Print decode DMA Descriptor of FPGA 5GNR Decoder device */ +/* Print decode DMA Descriptor of Vista Creek Decoder device. */ static void -print_dma_dec_desc_debug_info(union fpga_dma_desc *desc) +vc_5gnr_print_dma_dec_desc_debug_info(union vc_5gnr_dma_desc *desc) { rte_bbdev_log_debug("DMA response desc %p\n" - "\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")" - " | crcb_pass (%"PRIu32") | error(%"PRIu32")\n" - "\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | " - "bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n" - "\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") " - "| irq_en(%"PRIu32")\n" - "\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | " - "drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n" - "\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n" - "\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n" - "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")" - "| out_add (0x%08"PRIx32"%08"PRIx32")", - desc, - (uint32_t)desc->dec_req.done, - (uint32_t)desc->dec_req.iter, - (uint32_t)desc->dec_req.et_pass, - (uint32_t)desc->dec_req.crcb_pass, - (uint32_t)desc->dec_req.error, - (uint32_t)desc->dec_req.qm_idx, - (uint32_t)desc->dec_req.max_iter, - (uint32_t)desc->dec_req.bg_idx, - (uint32_t)desc->dec_req.harqin_en, - (uint32_t)desc->dec_req.zc, - (uint32_t)desc->dec_req.hbstroe_offset, - (uint32_t)desc->dec_req.num_null, - (uint32_t)desc->dec_req.irq_en, - (uint32_t)desc->dec_req.ncb, - (uint32_t)desc->dec_req.desc_idx, - (uint32_t)desc->dec_req.drop_crc24b, - (uint32_t)desc->dec_req.rv, - (uint32_t)desc->dec_req.crc24b_ind, - (uint32_t)desc->dec_req.et_dis, - (uint32_t)desc->dec_req.harq_input_length, - (uint32_t)desc->dec_req.rm_e, - (uint32_t)desc->dec_req.cbs_in_op, - (uint32_t)desc->dec_req.in_addr_hi, - (uint32_t)desc->dec_req.in_addr_lw, - (uint32_t)desc->dec_req.out_addr_hi, - (uint32_t)desc->dec_req.out_addr_lw); + "\t-- done(%"PRIu32") | iter(%"PRIu32") | et_pass(%"PRIu32")" + " | crcb_pass (%"PRIu32") | error(%"PRIu32")\n" + "\t-- qm_idx(%"PRIu32") | max_iter(%"PRIu32") | " + "bg_idx (%"PRIu32") | harqin_en(%"PRIu32") | zc(%"PRIu32")\n" + "\t-- hbstroe_offset(%"PRIu32") | num_null (%"PRIu32") " + "| irq_en(%"PRIu32")\n" + "\t-- ncb(%"PRIu32") | desc_idx (%"PRIu32") | " + "drop_crc24b(%"PRIu32") | RV (%"PRIu32")\n" + "\t-- crc24b_ind(%"PRIu32") | et_dis (%"PRIu32")\n" + "\t-- harq_input_length(%"PRIu32") | rm_e(%"PRIu32")\n" + "\t-- cbs_in_op(%"PRIu32") | in_add (0x%08"PRIx32"%08"PRIx32")" + "| out_add (0x%08"PRIx32"%08"PRIx32")", + desc, + (uint32_t)desc->dec_req.done, + (uint32_t)desc->dec_req.iter, + (uint32_t)desc->dec_req.et_pass, + (uint32_t)desc->dec_req.crcb_pass, + (uint32_t)desc->dec_req.error, + (uint32_t)desc->dec_req.qm_idx, + (uint32_t)desc->dec_req.max_iter, + (uint32_t)desc->dec_req.bg_idx, + (uint32_t)desc->dec_req.harqin_en, + (uint32_t)desc->dec_req.zc, + (uint32_t)desc->dec_req.hbstroe_offset, + (uint32_t)desc->dec_req.num_null, + (uint32_t)desc->dec_req.irq_en, + (uint32_t)desc->dec_req.ncb, + (uint32_t)desc->dec_req.desc_idx, + (uint32_t)desc->dec_req.drop_crc24b, + (uint32_t)desc->dec_req.rv, + (uint32_t)desc->dec_req.crc24b_ind, + (uint32_t)desc->dec_req.et_dis, + (uint32_t)desc->dec_req.harq_input_length, + (uint32_t)desc->dec_req.rm_e, + (uint32_t)desc->dec_req.cbs_in_op, + (uint32_t)desc->dec_req.in_addr_hi, + (uint32_t)desc->dec_req.in_addr_lw, + (uint32_t)desc->dec_req.out_addr_hi, + (uint32_t)desc->dec_req.out_addr_lw); uint32_t *word = (uint32_t *) desc; rte_bbdev_log_debug("%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n" "%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n%08"PRIx32"\n", @@ -143,9 +142,9 @@ print_dma_dec_desc_debug_info(union fpga_dma_desc *desc) word[4], word[5], word[6], word[7]); } -/* Print decode DMA Descriptor of FPGA 5GNR encoder device */ +/* Print decode DMA Descriptor of Vista Creek encoder device. */ static void -print_dma_enc_desc_debug_info(union fpga_dma_desc *desc) +vc_5gnr_print_dma_enc_desc_debug_info(union vc_5gnr_dma_desc *desc) { rte_bbdev_log_debug("DMA response desc %p\n" "%"PRIu32" %"PRIu32"\n" @@ -204,9 +203,9 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id * replaced with a queue ID and if it's not then * FPGA_5GNR_INVALID_HW_QUEUE_ID is returned. */ - for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { uint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base, - FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2)); + VC_5GNR_QUEUE_MAP + (q_id << 2)); rte_bbdev_log_debug("%s: queue ID: %u, registry queue ID: %u", dev->device->name, q_id, hw_q_id); @@ -216,8 +215,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id /* Clear queue register of found queue */ offset = FPGA_5GNR_FEC_RING_CTRL_REGS + (sizeof(struct fpga_5gnr_ring_ctrl_reg) * q_id); - fpga_ring_reg_write(d->mmio_base, - offset, ring_reg); + fpga_ring_reg_write(d->mmio_base, offset, ring_reg); ++hw_q_num; } } @@ -234,7 +232,7 @@ fpga_5gnr_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id return -EINVAL; } - ring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct fpga_dma_dec_desc); + ring_size = FPGA_5GNR_RING_MAX_SIZE * sizeof(struct vc_5gnr_dma_dec_desc); /* Enforce 32 byte alignment */ RTE_BUILD_BUG_ON((RTE_CACHE_LINE_SIZE % 32) != 0); @@ -369,9 +367,9 @@ fpga_5gnr_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_ /* Calculates number of queues assigned to device */ dev_info->max_num_queues = 0; - for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { + for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { uint32_t hw_q_id = fpga_5gnr_reg_read_32(d->mmio_base, - FPGA_5GNR_FEC_QUEUE_MAP + (q_id << 2)); + VC_5GNR_QUEUE_MAP + (q_id << 2)); if (hw_q_id != FPGA_5GNR_INVALID_HW_QUEUE_ID) dev_info->max_num_queues++; } @@ -396,11 +394,11 @@ fpga_5gnr_find_free_queue_idx(struct rte_bbdev *dev, struct fpga_5gnr_fec_device *d = dev->data->dev_private; uint64_t q_idx; uint8_t i = 0; - uint8_t range = FPGA_TOTAL_NUM_QUEUES >> 1; + uint8_t range = VC_5GNR_TOTAL_NUM_QUEUES >> 1; if (conf->op_type == RTE_BBDEV_OP_LDPC_ENC) { - i = FPGA_NUM_DL_QUEUES; - range = FPGA_TOTAL_NUM_QUEUES; + i = VC_5GNR_NUM_DL_QUEUES; + range = VC_5GNR_TOTAL_NUM_QUEUES; } for (; i < range; ++i) { @@ -447,7 +445,7 @@ fpga_5gnr_queue_setup(struct rte_bbdev *dev, uint16_t queue_id, q->q_idx = q_idx; /* Set ring_base_addr */ - q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); + q->vc_5gnr_ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id)); q->ring_ctrl_reg.ring_base_addr = d->sw_rings_phys + (d->sw_ring_size * queue_id); /* Allocate memory for Completion Head variable*/ @@ -663,7 +661,7 @@ fpga_5gnr_dev_interrupt_handler(void *cb_arg) uint8_t i; /* Scan queue assigned to this device */ - for (i = 0; i < FPGA_TOTAL_NUM_QUEUES; ++i) { + for (i = 0; i < VC_5GNR_TOTAL_NUM_QUEUES; ++i) { q_idx = 1ULL << i; if (d->q_bound_bit_map & q_idx) { queue_id = get_queue_id(dev->data, i); @@ -723,13 +721,12 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev) * mapped to FPGA IRQs in rte_intr_enable(). This is a 1:1 mapping where * the IRQ number is a direct translation to the queue number. * - * 63 (FPGA_NUM_INTR_VEC) event fds are created as rte_intr_enable() + * 63 (VC_5GNR_NUM_INTR_VEC) event fds are created as rte_intr_enable() * mapped the first IRQ to already created interrupt event file * descriptor (intr_handle->fd). */ - if (rte_intr_efd_enable(dev->intr_handle, FPGA_NUM_INTR_VEC)) { - rte_bbdev_log(ERR, "Failed to create fds for %u queues", - dev->data->num_queues); + if (rte_intr_efd_enable(dev->intr_handle, VC_5GNR_NUM_INTR_VEC)) { + rte_bbdev_log(ERR, "Failed to create fds for %u queues", dev->data->num_queues); return -1; } @@ -738,16 +735,14 @@ fpga_5gnr_intr_enable(struct rte_bbdev *dev) * It ensures that callback function assigned to that descriptor will * invoked when any FPGA queue issues interrupt. */ - for (i = 0; i < FPGA_NUM_INTR_VEC; ++i) { + for (i = 0; i < VC_5GNR_NUM_INTR_VEC; ++i) { if (rte_intr_efds_index_set(dev->intr_handle, i, rte_intr_fd_get(dev->intr_handle))) return -rte_errno; } - if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec", - dev->data->num_queues)) { - rte_bbdev_log(ERR, "Failed to allocate %u vectors", - dev->data->num_queues); + if (rte_intr_vec_list_alloc(dev->intr_handle, "intr_vec", dev->data->num_queues)) { + rte_bbdev_log(ERR, "Failed to allocate %u vectors", dev->data->num_queues); return -ENOMEM; } @@ -810,52 +805,52 @@ check_bit(uint32_t bitmap, uint32_t bitmask) return bitmap & bitmask; } -/* Print an error if a descriptor error has occurred. - * Return 0 on success, 1 on failure +/* Vista Creek 5GNR FPGA descriptor errors. + * Print an error if a descriptor error has occurred. + * Return 0 on success, 1 on failure. */ static inline int -check_desc_error(uint32_t error_code) { +vc_5gnr_check_desc_error(uint32_t error_code) { switch (error_code) { - case DESC_ERR_NO_ERR: + case VC_5GNR_DESC_ERR_NO_ERR: return 0; - case DESC_ERR_K_P_OUT_OF_RANGE: + case VC_5GNR_DESC_ERR_K_P_OUT_OF_RANGE: rte_bbdev_log(ERR, "Encode block size K' is out of range"); break; - case DESC_ERR_Z_C_NOT_LEGAL: + case VC_5GNR_DESC_ERR_Z_C_NOT_LEGAL: rte_bbdev_log(ERR, "Zc is illegal"); break; - case DESC_ERR_DESC_OFFSET_ERR: + case VC_5GNR_DESC_ERR_DESC_OFFSET_ERR: rte_bbdev_log(ERR, "Queue offset does not meet the expectation in the FPGA" ); break; - case DESC_ERR_DESC_READ_FAIL: + case VC_5GNR_DESC_ERR_DESC_READ_FAIL: rte_bbdev_log(ERR, "Unsuccessful completion for descriptor read"); break; - case DESC_ERR_DESC_READ_TIMEOUT: + case VC_5GNR_DESC_ERR_DESC_READ_TIMEOUT: rte_bbdev_log(ERR, "Descriptor read time-out"); break; - case DESC_ERR_DESC_READ_TLP_POISONED: + case VC_5GNR_DESC_ERR_DESC_READ_TLP_POISONED: rte_bbdev_log(ERR, "Descriptor read TLP poisoned"); break; - case DESC_ERR_HARQ_INPUT_LEN: + case VC_5GNR_DESC_ERR_HARQ_INPUT_LEN: rte_bbdev_log(ERR, "HARQ input length is invalid"); break; - case DESC_ERR_CB_READ_FAIL: + case VC_5GNR_DESC_ERR_CB_READ_FAIL: rte_bbdev_log(ERR, "Unsuccessful completion for code block"); break; - case DESC_ERR_CB_READ_TIMEOUT: + case VC_5GNR_DESC_ERR_CB_READ_TIMEOUT: rte_bbdev_log(ERR, "Code block read time-out"); break; - case DESC_ERR_CB_READ_TLP_POISONED: + case VC_5GNR_DESC_ERR_CB_READ_TLP_POISONED: rte_bbdev_log(ERR, "Code block read TLP poisoned"); break; - case DESC_ERR_HBSTORE_ERR: + case VC_5GNR_DESC_ERR_HBSTORE_ERR: rte_bbdev_log(ERR, "Hbstroe exceeds HARQ buffer size."); break; default: - rte_bbdev_log(ERR, "Descriptor error unknown error code %u", - error_code); + rte_bbdev_log(ERR, "Descriptor error unknown error code %u", error_code); break; } return 1; @@ -894,6 +889,7 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) } /** + * Vista Creek 5GNR FPGA * Set DMA descriptor for encode operation (1 Code Block) * * @param op @@ -918,8 +914,8 @@ get_k0(uint16_t n_cb, uint16_t z_c, uint8_t bg, uint8_t rv_index) * Number of CBs contained in one operation. */ static inline int -fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op, - struct fpga_dma_enc_desc *desc, struct rte_mbuf *input, +vc_5gnr_dma_desc_te_fill(struct rte_bbdev_enc_op *op, + struct vc_5gnr_dma_enc_desc *desc, struct rte_mbuf *input, struct rte_mbuf *output, uint16_t k_, uint16_t e, uint32_t in_offset, uint32_t out_offset, uint16_t desc_offset, uint8_t cbs_in_op) @@ -958,6 +954,7 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op, } /** + * Vista Creek 5GNR FPGA * Set DMA descriptor for decode operation (1 Code Block) * * @param op @@ -976,8 +973,8 @@ fpga_dma_desc_te_fill(struct rte_bbdev_enc_op *op, * Number of CBs contained in one operation. */ static inline int -fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, - struct fpga_dma_dec_desc *desc, +vc_5gnr_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, + struct vc_5gnr_dma_dec_desc *desc, struct rte_mbuf *input, struct rte_mbuf *output, uint16_t harq_in_length, uint32_t in_offset, uint32_t out_offset, @@ -1024,16 +1021,14 @@ fpga_dma_desc_ld_fill(struct rte_bbdev_dec_op *op, return 0; } -/* Validates LDPC encoder parameters */ +/* Validates LDPC encoder parameters for VC 5GNR FPGA. */ static inline int -validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) +vc_5gnr_validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) { struct rte_bbdev_op_ldpc_enc *ldpc_enc = &op->ldpc_enc; + int z_c, n_filler, K, Kp, q_m, n_cb, N, k0, crc24; + int32_t L, Lcb, cw, cw_rm, e; - if (op->mempool == NULL) { - rte_bbdev_log(ERR, "Invalid mempool pointer"); - return -1; - } if (ldpc_enc->input.data == NULL) { rte_bbdev_log(ERR, "Invalid input pointer"); return -1; @@ -1073,7 +1068,8 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) RTE_BBDEV_LDPC_MAX_CB_SIZE); return -1; } - int z_c = ldpc_enc->z_c; + + z_c = ldpc_enc->z_c; /* Check Zc is valid value */ if ((z_c > 384) || (z_c < 4)) { rte_bbdev_log(ERR, "Zc (%u) is out of range", z_c); @@ -1106,19 +1102,17 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) } } - int n_filler = ldpc_enc->n_filler; - int K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; - int Kp = K - n_filler; - int q_m = ldpc_enc->q_m; - int n_cb = ldpc_enc->n_cb; - int N = (ldpc_enc->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c; - int k0 = get_k0(n_cb, z_c, ldpc_enc->basegraph, - ldpc_enc->rv_index); - int crc24 = 0; - int32_t L, Lcb, cw, cw_rm; - int32_t e = ldpc_enc->cb_params.e; - if (check_bit(op->ldpc_enc.op_flags, - RTE_BBDEV_LDPC_CRC_24B_ATTACH)) + n_filler = ldpc_enc->n_filler; + K = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c; + Kp = K - n_filler; + q_m = ldpc_enc->q_m; + n_cb = ldpc_enc->n_cb; + N = (ldpc_enc->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c; + k0 = get_k0(n_cb, z_c, ldpc_enc->basegraph, ldpc_enc->rv_index); + crc24 = 0; + e = ldpc_enc->cb_params.e; + + if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH)) crc24 = 24; if (K < (int) (ldpc_enc->input.length * 8 + n_filler) + crc24) { @@ -1161,8 +1155,7 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) return -1; } /* K0 range check */ - if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) - && (k0 < (K - 2 * z_c)))) { + if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) { rte_bbdev_log(ERR, "K0 (%u) is out of range", k0); return -1; } @@ -1223,20 +1216,21 @@ validate_ldpc_enc_op(struct rte_bbdev_enc_op *op) else cw_rm = cw - n_filler; if (cw_rm <= 32) { - rte_bbdev_log(ERR, - "Invalid Ratematching"); + rte_bbdev_log(ERR, "Invalid Ratematching"); return -1; } return 0; } -/* Validates LDPC decoder parameters */ +/* Validates LDPC decoder parameters for VC 5GNR FPGA. */ static inline int -validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) +vc_5gnr_validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) { struct rte_bbdev_op_ldpc_dec *ldpc_dec = &op->ldpc_dec; - if (check_bit(ldpc_dec->op_flags, - RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) + int z_c, n_filler, K, Kp, q_m, n_cb, N, k0, crc24; + int32_t L, Lcb, cw, cw_rm, e; + + if (check_bit(ldpc_dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) return 0; if (ldpc_dec->input.data == NULL) { rte_bbdev_log(ERR, "Invalid input pointer"); @@ -1274,17 +1268,15 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) ldpc_dec->code_block_mode); return -1; } - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_DECODE_BYPASS)) { + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_DECODE_BYPASS)) { rte_bbdev_log(ERR, "Avoid LDPC Decode bypass"); return -1; } - int z_c = ldpc_dec->z_c; + + z_c = ldpc_dec->z_c; /* Check Zc is valid value */ if ((z_c > 384) || (z_c < 4)) { - rte_bbdev_log(ERR, - "Zc (%u) is out of range", - z_c); + rte_bbdev_log(ERR, "Zc (%u) is out of range", z_c); return -1; } if (z_c > 256) { @@ -1314,24 +1306,21 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) } } - int n_filler = ldpc_dec->n_filler; - int K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; - int Kp = K - n_filler; - int q_m = ldpc_dec->q_m; - int n_cb = ldpc_dec->n_cb; - int N = (ldpc_dec->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c; - int k0 = get_k0(n_cb, z_c, ldpc_dec->basegraph, - ldpc_dec->rv_index); - int crc24 = 0; - int32_t L, Lcb, cw, cw_rm; - int32_t e = ldpc_dec->cb_params.e; - if (check_bit(op->ldpc_dec.op_flags, - RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK)) + n_filler = ldpc_dec->n_filler; + K = (ldpc_dec->basegraph == 1 ? 22 : 10) * ldpc_dec->z_c; + Kp = K - n_filler; + q_m = ldpc_dec->q_m; + n_cb = ldpc_dec->n_cb; + N = (ldpc_dec->basegraph == 1 ? N_ZC_1 : N_ZC_2) * z_c; + k0 = get_k0(n_cb, z_c, ldpc_dec->basegraph, ldpc_dec->rv_index); + crc24 = 0; + e = ldpc_dec->cb_params.e; + + if (check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK)) crc24 = 24; if (ldpc_dec->code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { - rte_bbdev_log(ERR, - "TB mode not supported"); + rte_bbdev_log(ERR, "TB mode not supported"); return -1; } /* Enforce HARQ input length */ @@ -1353,34 +1342,24 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) /* K' range check */ if (Kp % 8 > 0) { - rte_bbdev_log(ERR, - "K' not byte aligned %u", - Kp); + rte_bbdev_log(ERR, "K' not byte aligned %u", Kp); return -1; } if ((crc24 > 0) && (Kp < 292)) { - rte_bbdev_log(ERR, - "Invalid CRC24 for small block %u", - Kp); + rte_bbdev_log(ERR, "Invalid CRC24 for small block %u", Kp); return -1; } if (Kp < 24) { - rte_bbdev_log(ERR, - "K' too small %u", - Kp); + rte_bbdev_log(ERR, "K' too small %u", Kp); return -1; } if (n_filler >= (K - 2 * z_c)) { - rte_bbdev_log(ERR, - "K - F invalid %u %u", - K, n_filler); + rte_bbdev_log(ERR, "K - F invalid %u %u", K, n_filler); return -1; } /* Ncb range check */ if (n_cb != N) { - rte_bbdev_log(ERR, - "Ncb (%u) is out of range K %d N %d", - n_cb, K, N); + rte_bbdev_log(ERR, "Ncb (%u) is out of range K %d N %d", n_cb, K, N); return -1; } /* Qm range check */ @@ -1388,34 +1367,26 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) RTE_BBDEV_LDPC_INTERLEAVER_BYPASS) && ((q_m == 0) || ((q_m > 2) && ((q_m % 2) == 1)) || (q_m > 8))) { - rte_bbdev_log(ERR, - "Qm (%u) is out of range", - q_m); + rte_bbdev_log(ERR, "Qm (%u) is out of range", q_m); return -1; } /* K0 range check */ - if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) - && (k0 < (K - 2 * z_c)))) { - rte_bbdev_log(ERR, - "K0 (%u) is out of range", - k0); + if (((k0 % z_c) > 0) || (k0 >= n_cb) || ((k0 >= (Kp - 2 * z_c)) && (k0 < (K - 2 * z_c)))) { + rte_bbdev_log(ERR, "K0 (%u) is out of range", k0); return -1; } /* E range check */ if (e <= RTE_MAX(32, z_c)) { - rte_bbdev_log(ERR, - "E is too small"); + rte_bbdev_log(ERR, "E is too small"); return -1; } if ((e > 0xFFFF)) { - rte_bbdev_log(ERR, - "E is too large"); + rte_bbdev_log(ERR, "E is too large"); return -1; } if (q_m > 0) { if (e % q_m > 0) { - rte_bbdev_log(ERR, - "E not multiple of qm %d", q_m); + rte_bbdev_log(ERR, "E not multiple of qm %d", q_m); return -1; } } @@ -1424,8 +1395,8 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) L = k0 + e; else L = k0 + e + n_filler; - Lcb = RTE_MIN(n_cb, RTE_MAX(L, - (int32_t) ldpc_dec->harq_combined_input.length)); + + Lcb = RTE_MIN(n_cb, RTE_MAX(L, (int32_t) ldpc_dec->harq_combined_input.length)); if (ldpc_dec->basegraph == 1) { if (Lcb <= 25 * z_c) cw = 25 * z_c; @@ -1455,8 +1426,7 @@ validate_ldpc_dec_op(struct rte_bbdev_dec_op *op) } cw_rm = cw - n_filler; if (cw_rm <= 32) { - rte_bbdev_log(ERR, - "Invalid Ratematching"); + rte_bbdev_log(ERR, "Invalid Ratematching"); return -1; } return 0; @@ -1627,7 +1597,7 @@ static inline int enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *op, uint16_t desc_offset) { - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *vc_5gnr_desc; int ret; uint8_t c, crc24_bits = 0; struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc; @@ -1641,8 +1611,7 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o uint16_t ring_offset; uint16_t K, k_; - - if (validate_ldpc_enc_op(op) == -1) { + if (vc_5gnr_validate_ldpc_enc_op(op) == -1) { rte_bbdev_log(ERR, "LDPC encoder validation rejected"); return -EINVAL; } @@ -1690,9 +1659,8 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o /* Offset into the ring */ ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); /* Setup DMA Descriptor */ - desc = q->ring_addr + ring_offset; - - ret = fpga_dma_desc_te_fill(op, &desc->enc_req, m_in, m_out, + vc_5gnr_desc = q->vc_5gnr_ring_addr + ring_offset; + ret = vc_5gnr_dma_desc_te_fill(op, &vc_5gnr_desc->enc_req, m_in, m_out, k_, e, in_offset, out_offset, ring_offset, c); if (unlikely(ret < 0)) return ret; @@ -1709,16 +1677,16 @@ enqueue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op *o } #ifdef RTE_LIBRTE_BBDEV_DEBUG - print_dma_enc_desc_debug_info(desc); + vc_5gnr_print_dma_enc_desc_debug_info(vc_5gnr_desc); #endif return 1; } static inline int -enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *op, +vc_5gnr_enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *op, uint16_t desc_offset) { - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *desc; int ret; uint16_t ring_offset; uint8_t c; @@ -1733,7 +1701,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o uint16_t out_offset = dec->hard_output.offset; uint32_t harq_offset = 0; - if (validate_ldpc_dec_op(op) == -1) { + if (vc_5gnr_validate_ldpc_dec_op(op) == -1) { rte_bbdev_log(ERR, "LDPC decoder validation rejected"); return -EINVAL; } @@ -1743,7 +1711,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o /* Setup DMA Descriptor */ ring_offset = ((q->tail + desc_offset) & q->sw_ring_wrap_mask); - desc = q->ring_addr + ring_offset; + desc = q->vc_5gnr_ring_addr + ring_offset; if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK)) { struct rte_mbuf *harq_in = dec->harq_combined_input.data; @@ -1776,6 +1744,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o /* Mark this dummy descriptor to be dropped by HW */ desc->dec_req.desc_idx = (ring_offset + 1) & q->sw_ring_wrap_mask; + return ret; /* Error or number of CB */ } @@ -1799,24 +1768,21 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o in_length = e; seg_total_left = dec->input.length; - if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) { - harq_in_length = RTE_MIN(dec->harq_combined_input.length, - (uint32_t)dec->n_cb); - } + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) + harq_in_length = RTE_MIN(dec->harq_combined_input.length, (uint32_t)dec->n_cb); if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) { - k0 = get_k0(dec->n_cb, dec->z_c, - dec->basegraph, dec->rv_index); + k0 = get_k0(dec->n_cb, dec->z_c, dec->basegraph, dec->rv_index); if (k0 > parity_offset) l = k0 + e; else l = k0 + e + dec->n_filler; - harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l), - dec->n_cb); + harq_out_length = RTE_MIN(RTE_MAX(harq_in_length, l), dec->n_cb); dec->harq_combined_output.length = harq_out_length; } mbuf_append(m_out_head, m_out, out_length); + if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE)) harq_offset = dec->harq_combined_input.offset; else if (check_bit(dec->op_flags, RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE)) @@ -1828,9 +1794,10 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o return -1; } - ret = fpga_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out, + ret = vc_5gnr_dma_desc_ld_fill(op, &desc->dec_req, m_in, m_out, harq_in_length, in_offset, out_offset, harq_offset, ring_offset, c); + if (unlikely(ret < 0)) return ret; /* Update lengths */ @@ -1844,7 +1811,7 @@ enqueue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op *o } #ifdef RTE_LIBRTE_BBDEV_DEBUG - print_dma_dec_desc_debug_info(desc); + vc_5gnr_print_dma_dec_desc_debug_info(desc); #endif return 1; @@ -1858,11 +1825,10 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, int32_t avail; int enqueued_cbs; struct fpga_5gnr_queue *q = q_data->queue_private; - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *vc_5gnr_desc; /* Check if queue is not full */ - if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == - q->head_free_desc)) + if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc)) return 0; /* Calculates available space */ @@ -1871,7 +1837,6 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, q->ring_ctrl_reg.ring_size + q->head_free_desc - q->tail - 1; for (i = 0; i < num; ++i) { - /* Check if there is available space for further * processing */ @@ -1893,9 +1858,9 @@ fpga_5gnr_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt * only when all previous CBs were already processed. */ - desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1) - & q->sw_ring_wrap_mask); - desc->enc_req.irq_en = q->irq_enable; + vc_5gnr_desc = q->vc_5gnr_ring_addr + + ((q->tail + total_enqueued_cbs - 1) & q->sw_ring_wrap_mask); + vc_5gnr_desc->enc_req.irq_en = q->irq_enable; fpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats); @@ -1914,7 +1879,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, int32_t avail; int enqueued_cbs; struct fpga_5gnr_queue *q = q_data->queue_private; - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *vc_5gnr_desc; /* Check if queue is not full */ if (unlikely(((q->tail + 1) & q->sw_ring_wrap_mask) == q->head_free_desc)) @@ -1933,7 +1898,7 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, if (unlikely(avail - 1 < 0)) break; avail -= 1; - enqueued_cbs = enqueue_ldpc_dec_one_op_cb(q, ops[i], + enqueued_cbs = vc_5gnr_enqueue_ldpc_dec_one_op_cb(q, ops[i], total_enqueued_cbs); if (enqueued_cbs < 0) @@ -1953,22 +1918,22 @@ fpga_5gnr_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, /* Set interrupt bit for last CB in enqueued ops. FPGA issues interrupt * only when all previous CBs were already processed. */ - desc = q->ring_addr + ((q->tail + total_enqueued_cbs - 1) - & q->sw_ring_wrap_mask); - desc->enc_req.irq_en = q->irq_enable; + vc_5gnr_desc = q->vc_5gnr_ring_addr + + ((q->tail + total_enqueued_cbs - 1) & q->sw_ring_wrap_mask); + vc_5gnr_desc->enc_req.irq_en = q->irq_enable; fpga_5gnr_dma_enqueue(q, total_enqueued_cbs, &q_data->queue_stats); return i; } static inline int -dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **op, +vc_5gnr_dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op **op, uint16_t desc_offset) { - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *desc; int desc_error; /* Set current desc */ - desc = q->ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); + desc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); /*check if done */ if (desc->enc_req.done == 0) @@ -1980,12 +1945,11 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op ** rte_bbdev_log_debug("DMA response desc %p", desc); #ifdef RTE_LIBRTE_BBDEV_DEBUG - print_dma_enc_desc_debug_info(desc); + vc_5gnr_print_dma_enc_desc_debug_info(desc); #endif - *op = desc->enc_req.op_addr; /* Check the descriptor error field, return 1 on error */ - desc_error = check_desc_error(desc->enc_req.error); + desc_error = vc_5gnr_check_desc_error(desc->enc_req.error); (*op)->status = desc_error << RTE_BBDEV_DATA_ERROR; return 1; @@ -1993,14 +1957,14 @@ dequeue_ldpc_enc_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_enc_op ** static inline int -dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **op, +vc_5gnr_dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op **op, uint16_t desc_offset) { - union fpga_dma_desc *desc; + union vc_5gnr_dma_desc *desc; int desc_error; + /* Set descriptor */ - desc = q->ring_addr + ((q->head_free_desc + desc_offset) - & q->sw_ring_wrap_mask); + desc = q->vc_5gnr_ring_addr + ((q->head_free_desc + desc_offset) & q->sw_ring_wrap_mask); /* Verify done bit is set */ if (desc->dec_req.done == 0) @@ -2010,7 +1974,7 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op ** rte_smp_rmb(); #ifdef RTE_LIBRTE_BBDEV_DEBUG - print_dma_dec_desc_debug_info(desc); + vc_5gnr_print_dma_dec_desc_debug_info(desc); #endif *op = desc->dec_req.op_addr; @@ -2023,14 +1987,19 @@ dequeue_ldpc_dec_one_op_cb(struct fpga_5gnr_queue *q, struct rte_bbdev_dec_op ** /* FPGA reports iterations based on round-up minus 1 */ (*op)->ldpc_dec.iter_count = desc->dec_req.iter + 1; + /* CRC Check criteria */ if (desc->dec_req.crc24b_ind && !(desc->dec_req.crcb_pass)) (*op)->status = 1 << RTE_BBDEV_CRC_ERROR; + /* et_pass = 0 when decoder fails */ (*op)->status |= !(desc->dec_req.et_pass) << RTE_BBDEV_SYNDROME_ERROR; + /* Check the descriptor error field, return 1 on error */ - desc_error = check_desc_error(desc->dec_req.error); + desc_error = vc_5gnr_check_desc_error(desc->dec_req.error); + (*op)->status |= desc_error << RTE_BBDEV_DATA_ERROR; + return 1; } @@ -2045,7 +2014,7 @@ fpga_5gnr_dequeue_ldpc_enc(struct rte_bbdev_queue_data *q_data, int ret; for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) { - ret = dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs); + ret = vc_5gnr_dequeue_ldpc_enc_one_op_cb(q, &ops[i], dequeued_cbs); if (ret < 0) break; @@ -2077,7 +2046,7 @@ fpga_5gnr_dequeue_ldpc_dec(struct rte_bbdev_queue_data *q_data, int ret; for (i = 0; (i < num) && (dequeued_cbs < avail); ++i) { - ret = dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs); + ret = vc_5gnr_dequeue_ldpc_dec_one_op_cb(q, &ops[i], dequeued_cbs); if (ret < 0) break; @@ -2167,9 +2136,8 @@ fpga_5gnr_fec_probe(struct rte_pci_driver *pci_drv, bbdev->data->dev_id, dev_name); struct fpga_5gnr_fec_device *d = bbdev->data->dev_private; - uint32_t version_id = fpga_5gnr_reg_read_32(d->mmio_base, - FPGA_5GNR_FEC_VERSION_ID); - rte_bbdev_log(INFO, "FEC FPGA RTL v%u.%u", + uint32_t version_id = fpga_5gnr_reg_read_32(d->mmio_base, FPGA_5GNR_FEC_VERSION_ID); + rte_bbdev_log(INFO, "Vista Creek FPGA RTL v%u.%u", ((uint16_t)(version_id >> 16)), ((uint16_t)version_id)); #ifdef RTE_LIBRTE_BBDEV_DEBUG @@ -2237,10 +2205,8 @@ fpga_5gnr_set_default_conf(struct rte_fpga_5gnr_fec_conf *def_conf) def_conf->ul_load_balance = 64; } -/* Initial configuration of FPGA 5GNR FEC device */ -int -rte_fpga_5gnr_fec_configure(const char *dev_name, - const struct rte_fpga_5gnr_fec_conf *conf) +/* Initial configuration of Vista Creek device. */ +static int vc_5gnr_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf) { uint32_t payload_32, address; uint16_t payload_16; @@ -2259,8 +2225,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, struct fpga_5gnr_fec_device *d = bbdev->data->dev_private; if (conf == NULL) { - rte_bbdev_log(ERR, - "FPGA Configuration was not provided. Default configuration will be loaded."); + rte_bbdev_log(ERR, "VC FPGA Configuration was not provided."); + rte_bbdev_log(ERR, "Default configuration will be loaded."); fpga_5gnr_set_default_conf(&def_conf); conf = &def_conf; } @@ -2271,13 +2237,13 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, * [15:8]: DL weight */ payload_16 = (conf->dl_bandwidth << 8) | conf->ul_bandwidth; - address = FPGA_5GNR_FEC_CONFIGURATION; + address = VC_5GNR_CONFIGURATION; fpga_5gnr_reg_write_16(d->mmio_base, address, payload_16); /* Clear all queues registers */ payload_32 = FPGA_5GNR_INVALID_HW_QUEUE_ID; - for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { - address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + VC_5GNR_QUEUE_MAP; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); } @@ -2285,7 +2251,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, * If PF mode is enabled allocate all queues for PF only. * * For VF mode each VF can have different number of UL and DL queues. - * Total number of queues to configure cannot exceed FPGA + * Total number of queues to configure cannot exceed VC FPGA * capabilities - 64 queues - 32 queues for UL and 32 queues for DL. * Queues mapping is done according to configuration: * @@ -2337,8 +2303,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, */ if (conf->pf_mode_en) { payload_32 = 0x1; - for (q_id = 0; q_id < FPGA_TOTAL_NUM_QUEUES; ++q_id) { - address = (q_id << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + for (q_id = 0; q_id < VC_5GNR_TOTAL_NUM_QUEUES; ++q_id) { + address = (q_id << 2) + VC_5GNR_QUEUE_MAP; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); } } else { @@ -2353,21 +2319,20 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, * Check if total number of queues to configure does not exceed * FPGA capabilities (64 queues - 32 UL and 32 DL queues) */ - if ((total_ul_q_id > FPGA_NUM_UL_QUEUES) || - (total_dl_q_id > FPGA_NUM_DL_QUEUES) || - (total_q_id > FPGA_TOTAL_NUM_QUEUES)) { + if ((total_ul_q_id > VC_5GNR_NUM_UL_QUEUES) || + (total_dl_q_id > VC_5GNR_NUM_DL_QUEUES) || + (total_q_id > VC_5GNR_TOTAL_NUM_QUEUES)) { rte_bbdev_log(ERR, - "FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u", + "VC 5GNR FPGA Configuration failed. Too many queues to configure: UL_Q %u, DL_Q %u, FPGA_Q %u", total_ul_q_id, total_dl_q_id, - FPGA_TOTAL_NUM_QUEUES); + VC_5GNR_TOTAL_NUM_QUEUES); return -EINVAL; } total_ul_q_id = 0; for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { for (q_id = 0; q_id < conf->vf_ul_queues_number[vf_id]; ++q_id, ++total_ul_q_id) { - address = (total_ul_q_id << 2) + - FPGA_5GNR_FEC_QUEUE_MAP; + address = (total_ul_q_id << 2) + VC_5GNR_QUEUE_MAP; payload_32 = ((0x80 + vf_id) << 16) | 0x1; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); @@ -2377,8 +2342,8 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, for (vf_id = 0; vf_id < FPGA_5GNR_FEC_NUM_VFS; ++vf_id) { for (q_id = 0; q_id < conf->vf_dl_queues_number[vf_id]; ++q_id, ++total_dl_q_id) { - address = ((total_dl_q_id + FPGA_NUM_UL_QUEUES) - << 2) + FPGA_5GNR_FEC_QUEUE_MAP; + address = ((total_dl_q_id + VC_5GNR_NUM_UL_QUEUES) + << 2) + VC_5GNR_QUEUE_MAP; payload_32 = ((0x80 + vf_id) << 16) | 0x1; fpga_5gnr_reg_write_32(d->mmio_base, address, payload_32); @@ -2401,8 +2366,7 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, address = FPGA_5GNR_FEC_QUEUE_PF_VF_MAP_DONE; fpga_5gnr_reg_write_8(d->mmio_base, address, payload_8); - rte_bbdev_log_debug("PF FPGA 5GNR FEC configuration complete for %s", - dev_name); + rte_bbdev_log_debug("PF Vista Creek 5GNR FPGA configuration complete for %s", dev_name); #ifdef RTE_LIBRTE_BBDEV_DEBUG print_static_reg_debug_info(d->mmio_base); @@ -2410,11 +2374,27 @@ rte_fpga_5gnr_fec_configure(const char *dev_name, return 0; } +int rte_fpga_5gnr_fec_configure(const char *dev_name, const struct rte_fpga_5gnr_fec_conf *conf) +{ + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name); + if (bbdev == NULL) { + rte_bbdev_log(ERR, "Invalid dev_name (%s), or device is not yet initialised", + dev_name); + return -ENODEV; + } + struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(bbdev->device); + printf("Configure dev id %x\n", pci_dev->id.device_id); + if (pci_dev->id.device_id == VC_5GNR_PF_DEVICE_ID) + return vc_5gnr_configure(dev_name, conf); + + rte_bbdev_log(ERR, "Invalid device_id (%d)", pci_dev->id.device_id); + return -ENODEV; +} + /* FPGA 5GNR FEC PCI PF address map */ static struct rte_pci_id pci_id_fpga_5gnr_fec_pf_map[] = { { - RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID, - FPGA_5GNR_FEC_PF_DEVICE_ID) + RTE_PCI_DEVICE(VC_5GNR_VENDOR_ID, VC_5GNR_PF_DEVICE_ID) }, {.device_id = 0}, }; @@ -2429,8 +2409,7 @@ static struct rte_pci_driver fpga_5gnr_fec_pci_pf_driver = { /* FPGA 5GNR FEC PCI VF address map */ static struct rte_pci_id pci_id_fpga_5gnr_fec_vf_map[] = { { - RTE_PCI_DEVICE(FPGA_5GNR_FEC_VENDOR_ID, - FPGA_5GNR_FEC_VF_DEVICE_ID) + RTE_PCI_DEVICE(VC_5GNR_VENDOR_ID, VC_5GNR_VF_DEVICE_ID) }, {.device_id = 0}, }; diff --git a/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h new file mode 100644 index 000000000000..47fb43199f86 --- /dev/null +++ b/drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2022 Intel Corporation + */ + +#ifndef _VC_5GNR_PMD_H_ +#define _VC_5GNR_PMD_H_ + +#include +#include + +/* VC 5GNR FPGA FEC PCI vendor & device IDs. */ +#define VC_5GNR_VENDOR_ID (0x8086) +#define VC_5GNR_PF_DEVICE_ID (0x0D8F) +#define VC_5GNR_VF_DEVICE_ID (0x0D90) + +#define VC_5GNR_NUM_UL_QUEUES (32) +#define VC_5GNR_NUM_DL_QUEUES (32) +#define VC_5GNR_TOTAL_NUM_QUEUES (VC_5GNR_NUM_UL_QUEUES + VC_5GNR_NUM_DL_QUEUES) +#define VC_5GNR_NUM_INTR_VEC (VC_5GNR_TOTAL_NUM_QUEUES - RTE_INTR_VEC_RXTX_OFFSET) + +/* VC 5GNR Ring size is in 256 bits (32 bytes) units. */ +#define VC_5GNR_RING_DESC_LEN_UNIT_BYTES (32) + +/* Align DMA descriptors to 256 bytes - cache-aligned. */ +#define VC_5GNR_RING_DESC_ENTRY_LENGTH (8) + +/* VC 5GNR FPGA Register mapping on BAR0. */ +enum { + VC_5GNR_CONFIGURATION = 0x00000004, /* len: 2B. */ + VC_5GNR_QUEUE_MAP = 0x00000040 /* len: 256B. */ +}; + +/* VC 5GNR FPGA FEC DESCRIPTOR ERROR. */ +enum { + VC_5GNR_DESC_ERR_NO_ERR = 0x0, + VC_5GNR_DESC_ERR_K_P_OUT_OF_RANGE = 0x1, + VC_5GNR_DESC_ERR_Z_C_NOT_LEGAL = 0x2, + VC_5GNR_DESC_ERR_DESC_OFFSET_ERR = 0x3, + VC_5GNR_DESC_ERR_DESC_READ_FAIL = 0x8, + VC_5GNR_DESC_ERR_DESC_READ_TIMEOUT = 0x9, + VC_5GNR_DESC_ERR_DESC_READ_TLP_POISONED = 0xA, + VC_5GNR_DESC_ERR_HARQ_INPUT_LEN = 0xB, + VC_5GNR_DESC_ERR_CB_READ_FAIL = 0xC, + VC_5GNR_DESC_ERR_CB_READ_TIMEOUT = 0xD, + VC_5GNR_DESC_ERR_CB_READ_TLP_POISONED = 0xE, + VC_5GNR_DESC_ERR_HBSTORE_ERR = 0xF +}; + +/* VC 5GNR FPGA FEC DMA Encoding Request Descriptor. */ +struct __rte_packed vc_5gnr_dma_enc_desc { + uint32_t done:1, + rsrvd0:7, + error:4, + rsrvd1:4, + num_null:10, + rsrvd2:6; + uint32_t ncb:15, + rsrvd3:1, + k0:16; + uint32_t irq_en:1, + crc_en:1, + rsrvd4:1, + qm_idx:3, + bg_idx:1, + zc:9, + desc_idx:10, + rsrvd5:6; + uint16_t rm_e; + uint16_t k_; + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /** Virtual addresses used to retrieve SW context info. */ + void *op_addr; + /** Stores information about total number of Code Blocks + * in currently processed Transport Block. + */ + uint64_t cbs_in_op; + }; + + uint8_t sw_ctxt[VC_5GNR_RING_DESC_LEN_UNIT_BYTES * + (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + +/* VC 5GNR FPGA DPC FEC DMA Decoding Request Descriptor. */ +struct __rte_packed vc_5gnr_dma_dec_desc { + uint32_t done:1, + iter:5, + et_pass:1, + crcb_pass:1, + error:4, + qm_idx:3, + max_iter:5, + bg_idx:1, + rsrvd0:1, + harqin_en:1, + zc:9; + uint32_t hbstroe_offset:22, + num_null:10; + uint32_t irq_en:1, + ncb:15, + desc_idx:10, + drop_crc24b:1, + crc24b_ind:1, + rv:2, + et_dis:1, + rsrvd2:1; + uint32_t harq_input_length:16, + rm_e:16; /**< the inbound data byte length. */ + uint32_t out_addr_lw; + uint32_t out_addr_hi; + uint32_t in_addr_lw; + uint32_t in_addr_hi; + + union { + struct { + /** Virtual addresses used to retrieve SW context info. */ + void *op_addr; + /** Stores information about total number of Code Blocks + * in currently processed Transport Block. + */ + uint8_t cbs_in_op; + }; + + uint32_t sw_ctxt[8 * (VC_5GNR_RING_DESC_ENTRY_LENGTH - 1)]; + }; +}; + +/* Vista Creek 5GNR DMA Descriptor. */ +union vc_5gnr_dma_desc { + struct vc_5gnr_dma_enc_desc enc_req; + struct vc_5gnr_dma_dec_desc dec_req; +}; + +#endif /* _VC_5GNR_PMD_H_ */ -- 2.37.1