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[204.195.123.141]) by smtp.gmail.com with ESMTPSA id q65-20020a17090a17c700b0028be0ec6e76sm5016234pja.28.2024.01.19.14.30.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 14:30:43 -0800 (PST) Date: Fri, 19 Jan 2024 14:30:41 -0800 From: Stephen Hemminger <stephen@networkplumber.org> To: Mattias =?UTF-8?B?UsO2bm5ibG9t?= <hofors@lysator.liu.se> Cc: Bruce Richardson <bruce.richardson@intel.com>, dev@dpdk.org, Jerin Jacob <jerinj@marvell.com> Subject: Re: [RFC PATCH] eventdev: ensure 16-byte alignment for events Message-ID: <20240119143041.59802717@hermes.local> In-Reply-To: <fcd11d73-d098-4734-9540-944aff73ed71@lysator.liu.se> References: <20231005115101.12276-1-bruce.richardson@intel.com> <fcd11d73-d098-4734-9540-944aff73ed71@lysator.liu.se> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org On Fri, 6 Oct 2023 14:15:00 +0200 Mattias R=C3=B6nnblom <hofors@lysator.liu.se> wrote: > On 2023-10-05 13:51, Bruce Richardson wrote: > > The event structure in DPDK is 16-bytes in size, and events are > > regularly passed as parameters directly rather than being passed as > > pointers. =20 >=20 > When are events passed by-value, rather than by-reference? There are no=20 > such examples in the public eventdev API. >=20 > To help compiler optimize correctly, we can explicitly request > > 16-byte alignment for events, which means that we should be able > > to do aligned vector loads/stores (e.g. with SSE or Neon) when working > > with those events. > > =20 >=20 > That change is both helping and sabotaging the optimizer's work. Now=20 > every stack allocation needs to be 2-byte aligned - in DPDK code, and in= =20 > the application. >=20 > The effect this change has on an eventdev app using DSW is a ~3=20 > cycle/event performance degradation on an AMD Zen 3 system, and a ~4=20 > cycle/event performance degradation on a Skylake-generation Intel CPU. >=20 > What scenarios do you have in mind, where this change would improve the=20 > generated code? Something where there are no unaligned loads available=20 > in the ISA, or they are much slower than their aligned counterparts? >=20 > When I looked into the same issue for the DPDK IP checksumming routines,= =20 > there basically were no such. Not that I could find. >=20 > > Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Don't understand what the issue is. Isn't the event structure typically on stack. Adding padding there would not help.