From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6137843922; Mon, 22 Jan 2024 05:02:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9303A40A6B; Mon, 22 Jan 2024 05:01:55 +0100 (CET) Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by mails.dpdk.org (Postfix) with ESMTP id 9891C409FA for ; Mon, 22 Jan 2024 05:01:51 +0100 (CET) Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4TJGjF1C8mzsWK4; Mon, 22 Jan 2024 12:00:49 +0800 (CST) Received: from dggpeml500024.china.huawei.com (unknown [7.185.36.10]) by mail.maildlp.com (Postfix) with ESMTPS id 0FCDF1400FD; Mon, 22 Jan 2024 12:01:49 +0800 (CST) Received: from localhost.localdomain (10.50.165.33) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 22 Jan 2024 12:01:48 +0800 From: Chengwen Feng To: , , , CC: Subject: [PATCH 01/12] eal: introduce more macro for bit definition Date: Mon, 22 Jan 2024 03:57:51 +0000 Message-ID: <20240122035802.31491-2-fengchengwen@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240122035802.31491-1-fengchengwen@huawei.com> References: <20231121122651.7078-1-fengchengwen@huawei.com> <20240122035802.31491-1-fengchengwen@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.50.165.33] X-ClientProxiedBy: dggems702-chm.china.huawei.com (10.3.19.179) To dggpeml500024.china.huawei.com (7.185.36.10) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Introduce macros: RTE_MBIT64/RTE_MBIT32, RTE_GENMASK64/RTE_GENMASK32, and RTE_FIELD_GET64/RTE_FIELD_GET32. Signed-off-by: Chengwen Feng --- lib/eal/include/rte_bitops.h | 64 ++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h index 6bd8bae21a..e1f3c4b195 100644 --- a/lib/eal/include/rte_bitops.h +++ b/lib/eal/include/rte_bitops.h @@ -39,6 +39,70 @@ extern "C" { */ #define RTE_BIT32(nr) (UINT32_C(1) << (nr)) +/** + * Get the uint64_t value for a multiple bits set. + * + * @param val + * The value may not all 1s. + * @param nr + * The bit number in range of 0 to (64 - width of val). + */ +#define RTE_MBIT64(val, nr) (UINT64_C(val) << (nr)) + +/** + * Get the uint32_t value for a multiple bits set. + * + * @param val + * The value may not all 1s. + * @param nr + * The bit number in range of 0 to (32 - width of val). + */ +#define RTE_MBIT32(val, nr) (UINT32_C(val) << (nr)) + +/** + * Generate a contiguous 64bit bitmask starting at bit position low + * and ending at position high. + * + * @param high + * High bit position. + * @param low + * Low bit position. + */ +#define RTE_GENMASK64(high, low) (((~UINT64_C(0)) << (low)) & (~UINT64_C(0) >> (63u - (high)))) + +/** + * Generate a contiguous 32bit bitmask starting at bit position low + * and ending at position high. + * + * @param high + * High bit position. + * @param low + * Low bit position. + */ +#define RTE_GENMASK32(high, low) (((~UINT32_C(0)) << (low)) & (~UINT32_C(0) >> (31u - (high)))) + +/** + * Extract a 64bit field element. + * + * @param mask + * shifted mask. + * @param reg + * value of entire bitfield. + */ +#define RTE_FIELD_GET64(mask, reg) \ + (typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask)) + +/** + * Extract a 32bit field element. + * + * @param mask + * shifted mask. + * @param reg + * value of entire bitfield. + */ +#define RTE_FIELD_GET32(mask, reg) \ + (typeof(mask))(((reg) & (mask)) >> rte_ctz32(mask)) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** -- 2.17.1