From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8774A43AA1; Wed, 7 Feb 2024 18:17:19 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3FDE342DF9; Wed, 7 Feb 2024 18:17:15 +0100 (CET) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by mails.dpdk.org (Postfix) with ESMTP id 5E0644026E; Wed, 7 Feb 2024 18:17:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707326233; x=1738862233; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s420qxgENsxnrl2g/vl8+b6q2lMKfU8gv8OKHFeecX0=; b=ayOvxjSL+lItv5bgKcHas8lq4yb3WNMq8SFKFXblQiqWYix93F068BXt IuocfNkNPFgUgTfiX75DiWRz2OVZYNcZwRSA3AJ+HzG/GpanMlBI9YmS1 n0QBYk3JYF7Qhu5oAmLAoiSNHcDKyexmgqXisXC7zztSFx+VarAX+LQ1e Y7ij/ltTPMHqOP2qSEUfXvEAiNTAuicC+UZTNu8rmdn02AEqV4d3UnzFO A8eAB3UuipTUeHMHsw8TSjFDOoGKqtd5Az+K6bT9dYeAcq7TbjlAC26yG pSjWSpt21GjfppAkCBB74VixUoVkiCwGuLTYjEPYSpvP5bLlW2gKSBhTV Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10977"; a="1185783" X-IronPort-AV: E=Sophos;i="6.05,251,1701158400"; d="scan'208";a="1185783" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2024 09:17:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,251,1701158400"; d="scan'208";a="1410876" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by fmviesa007.fm.intel.com with ESMTP; 07 Feb 2024 09:17:10 -0800 From: Hernan Vargas To: dev@dpdk.org, gakhil@marvell.com, trix@redhat.com, maxime.coquelin@redhat.com Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com, Hernan Vargas , stable@dpdk.org Subject: [PATCH v6 1/6] doc: fix fpga 5gnr configuration values Date: Wed, 7 Feb 2024 09:13:45 -0800 Message-Id: <20240207171350.242156-2-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20240207171350.242156-1-hernan.vargas@intel.com> References: <20240207171350.242156-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org flr_timeout was removed from the code a while ago, updating doc. Fix minor typo in 5GNR example. Fixes: 2d4306438c92 ("baseband/fpga_5gnr_fec: add configure function") Cc: stable@dpdk.org Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- doc/guides/bbdevs/fpga_5gnr_fec.rst | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst index 956dd6bed560..99fc936829a8 100644 --- a/doc/guides/bbdevs/fpga_5gnr_fec.rst +++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst @@ -100,7 +100,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure: uint8_t dl_bandwidth; uint8_t ul_load_balance; uint8_t dl_load_balance; - uint16_t flr_time_out; }; - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and @@ -126,10 +125,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure: If all hardware queues exceeds the watermark, no code blocks will be streamed in from UL/DL code block FIFO. -- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The - time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for - the FLR time out then set this setting to 0x262=610. - An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown below: @@ -154,7 +149,7 @@ below: /* setup FPGA PF */ ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf); TEST_ASSERT_SUCCESS(ret, - "Failed to configure 4G FPGA PF for bbdev %s", + "Failed to configure 5GNR FPGA PF for bbdev %s", info->dev_name); -- 2.37.1