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Thu, 08 Feb 2024 01:00:29 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 8 Feb 2024 01:00:27 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 8 Feb 2024 01:00:27 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id EFA753F708E; Thu, 8 Feb 2024 01:00:25 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH 11/13] net/cnxk: fix check cookies for multi-seg offload Date: Thu, 8 Feb 2024 14:29:54 +0530 Message-ID: <20240208085956.1741174-11-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240208085956.1741174-1-ndabilpuram@marvell.com> References: <20240208085956.1741174-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 5H8K7-HFkRGo0bNrNTwB8hKrScc-RQZz X-Proofpoint-GUID: 5H8K7-HFkRGo0bNrNTwB8hKrScc-RQZz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-08_01,2024-02-07_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Fix missing check cookies with multi-seg offload case Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K") Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_tx.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index 9721b7584a..a995696e66 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1863,6 +1863,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, len -= dlen; sg_u = sg_u | ((uint64_t)dlen); + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); + nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; @@ -1888,6 +1891,9 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, slist++; } m->next = NULL; + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); + m = m_next; } while (nb_segs); @@ -1911,8 +1917,11 @@ cn10k_nix_prepare_mseg_vec(struct rte_mbuf *m, uint64_t *cmd, uint64x2_t *cmd0, union nix_send_hdr_w0_u sh; union nix_send_sg_s sg; - if (m->nb_segs == 1) + if (m->nb_segs == 1) { + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(m->pool, (void **)&m, 1, 0); return; + } sh.u = vgetq_lane_u64(cmd0[0], 0); sg.u = vgetq_lane_u64(cmd1[0], 0); @@ -1972,6 +1981,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq, *data128 |= ((__uint128_t)7) << *shift; *shift += 3; + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(mbufs[0]->pool, (void **)&mbufs[0], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[1]->pool, (void **)&mbufs[1], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[2]->pool, (void **)&mbufs[2], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[3]->pool, (void **)&mbufs[3], 1, 0); return 1; } } @@ -1990,6 +2004,11 @@ cn10k_nix_prep_lmt_mseg_vector(struct cn10k_eth_txq *txq, vst1q_u64(lmt_addr + 10, cmd2[j + 1]); vst1q_u64(lmt_addr + 12, cmd1[j + 1]); vst1q_u64(lmt_addr + 14, cmd3[j + 1]); + + /* Mark mempool object as "put" since it is freed by NIX */ + RTE_MEMPOOL_CHECK_COOKIES(mbufs[j]->pool, (void **)&mbufs[j], 1, 0); + RTE_MEMPOOL_CHECK_COOKIES(mbufs[j + 1]->pool, + (void **)&mbufs[j + 1], 1, 0); } else if (flags & NIX_TX_NEED_EXT_HDR) { /* EXT header take 3 each, space for 2 segs.*/ cn10k_nix_prepare_mseg_vec(mbufs[j], -- 2.25.1