From: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
To: dev@dpdk.org
Subject: [PATCH 2/3] pipeline: optimize conversion between IPv4 and IPv6 addresses
Date: Tue, 13 Feb 2024 16:57:36 +0000 [thread overview]
Message-ID: <20240213165737.1534180-3-cristian.dumitrescu@intel.com> (raw)
In-Reply-To: <20240213165737.1534180-1-cristian.dumitrescu@intel.com>
Enhanced the move instruction to detect and optimize the conversion
between 128-bit numbers (IPv6 addresses) and 64-bit (upper or lower
part of IPv6 addresses) or 32-bit numbers (IPv4 addresses).
Signed-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
---
lib/pipeline/rte_swx_pipeline.c | 56 ++++++++++++++++++++++++
lib/pipeline/rte_swx_pipeline_internal.h | 52 ++++++++++++++++++++++
2 files changed, 108 insertions(+)
diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c
index 12f335005d..147c1c2ad4 100644
--- a/lib/pipeline/rte_swx_pipeline.c
+++ b/lib/pipeline/rte_swx_pipeline.c
@@ -3234,8 +3234,16 @@ instr_mov_translate(struct rte_swx_pipeline *p,
instr->type = INSTR_MOV_DMA;
if (fdst->n_bits == 128 && fsrc->n_bits == 128)
instr->type = INSTR_MOV_128;
+
+ if (fdst->n_bits == 128 && fsrc->n_bits == 64)
+ instr->type = INSTR_MOV_128_64;
+ if (fdst->n_bits == 64 && fsrc->n_bits == 128)
+ instr->type = INSTR_MOV_64_128;
+
if (fdst->n_bits == 128 && fsrc->n_bits == 32)
instr->type = INSTR_MOV_128_32;
+ if (fdst->n_bits == 32 && fsrc->n_bits == 128)
+ instr->type = INSTR_MOV_32_128;
}
instr->mov.dst.struct_id = (uint8_t)dst_struct_id;
@@ -3335,6 +3343,30 @@ instr_mov_128_exec(struct rte_swx_pipeline *p)
thread_ip_inc(p);
}
+static inline void
+instr_mov_128_64_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ __instr_mov_128_64_exec(p, t, ip);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
+static inline void
+instr_mov_64_128_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ __instr_mov_64_128_exec(p, t, ip);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
static inline void
instr_mov_128_32_exec(struct rte_swx_pipeline *p)
{
@@ -3347,6 +3379,18 @@ instr_mov_128_32_exec(struct rte_swx_pipeline *p)
thread_ip_inc(p);
}
+static inline void
+instr_mov_32_128_exec(struct rte_swx_pipeline *p)
+{
+ struct thread *t = &p->threads[p->thread_id];
+ struct instruction *ip = t->ip;
+
+ __instr_mov_32_128_exec(p, t, ip);
+
+ /* Thread. */
+ thread_ip_inc(p);
+}
+
static inline void
instr_mov_i_exec(struct rte_swx_pipeline *p)
{
@@ -7523,7 +7567,10 @@ static instr_exec_t instruction_table[] = {
[INSTR_MOV_HH] = instr_mov_hh_exec,
[INSTR_MOV_DMA] = instr_mov_dma_exec,
[INSTR_MOV_128] = instr_mov_128_exec,
+ [INSTR_MOV_128_64] = instr_mov_128_64_exec,
+ [INSTR_MOV_64_128] = instr_mov_64_128_exec,
[INSTR_MOV_128_32] = instr_mov_128_32_exec,
+ [INSTR_MOV_32_128] = instr_mov_32_128_exec,
[INSTR_MOV_I] = instr_mov_i_exec,
[INSTR_MOVH] = instr_movh_exec,
@@ -11850,7 +11897,10 @@ instr_type_to_name(struct instruction *instr)
case INSTR_MOV_HH: return "INSTR_MOV_HH";
case INSTR_MOV_DMA: return "INSTR_MOV_DMA";
case INSTR_MOV_128: return "INSTR_MOV_128";
+ case INSTR_MOV_128_64: return "INSTR_MOV_128_64";
+ case INSTR_MOV_64_128: return "INSTR_MOV_64_128";
case INSTR_MOV_128_32: return "INSTR_MOV_128_32";
+ case INSTR_MOV_32_128: return "INSTR_MOV_32_128";
case INSTR_MOV_I: return "INSTR_MOV_I";
case INSTR_MOVH: return "INSTR_MOVH";
@@ -12921,7 +12971,10 @@ static instruction_export_t export_table[] = {
[INSTR_MOV_HH] = instr_mov_export,
[INSTR_MOV_DMA] = instr_mov_export,
[INSTR_MOV_128] = instr_mov_export,
+ [INSTR_MOV_128_64] = instr_mov_export,
+ [INSTR_MOV_64_128] = instr_mov_export,
[INSTR_MOV_128_32] = instr_mov_export,
+ [INSTR_MOV_32_128] = instr_mov_export,
[INSTR_MOV_I] = instr_mov_export,
[INSTR_MOVH] = instr_movh_export,
@@ -13152,7 +13205,10 @@ instr_type_to_func(struct instruction *instr)
case INSTR_MOV_HH: return "__instr_mov_hh_exec";
case INSTR_MOV_DMA: return "__instr_mov_dma_exec";
case INSTR_MOV_128: return "__instr_mov_128_exec";
+ case INSTR_MOV_128_64: return "__instr_mov_128_64_exec";
+ case INSTR_MOV_64_128: return "__instr_mov_64_128_exec";
case INSTR_MOV_128_32: return "__instr_mov_128_32_exec";
+ case INSTR_MOV_32_128: return "__instr_mov_32_128_exec";
case INSTR_MOV_I: return "__instr_mov_i_exec";
case INSTR_MOVH: return "__instr_movh_exec";
diff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h
index 7ae7622329..f5a64e0fe1 100644
--- a/lib/pipeline/rte_swx_pipeline_internal.h
+++ b/lib/pipeline/rte_swx_pipeline_internal.h
@@ -344,7 +344,10 @@ enum instruction_type {
INSTR_MOV_HH, /* dst = H, src = H; size(dst) <= 64 bits, size(src) <= 64 bits. */
INSTR_MOV_DMA, /* dst and src in NBO format. */
INSTR_MOV_128, /* dst and src in NBO format, size(dst) = size(src) = 128 bits. */
+ INSTR_MOV_128_64, /* dst and src in NBO format, size(dst) = 128 bits, size(src) = 64 b. */
+ INSTR_MOV_64_128, /* dst and src in NBO format, size(dst) = 64 bits, size(src) = 128 b. */
INSTR_MOV_128_32, /* dst and src in NBO format, size(dst) = 128 bits, size(src) = 32 b. */
+ INSTR_MOV_32_128, /* dst and src in NBO format, size(dst) = 32 bits, size(src) = 128 b. */
INSTR_MOV_I, /* dst = HMEF, src = I; size(dst) <= 64 bits. */
/* movh dst src
@@ -2682,6 +2685,39 @@ __instr_mov_128_exec(struct rte_swx_pipeline *p __rte_unused,
dst64_ptr[1] = src64_ptr[1];
}
+static inline void
+__instr_mov_128_64_exec(struct rte_swx_pipeline *p __rte_unused,
+ struct thread *t,
+ const struct instruction *ip)
+{
+ uint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset;
+ uint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset;
+
+ uint64_t *dst64 = (uint64_t *)dst;
+ uint64_t *src64 = (uint64_t *)src;
+
+ TRACE("[Thread %2u] mov (128 <- 64)\n", p->thread_id);
+
+ dst64[0] = 0;
+ dst64[1] = src64[0];
+}
+
+static inline void
+__instr_mov_64_128_exec(struct rte_swx_pipeline *p __rte_unused,
+ struct thread *t,
+ const struct instruction *ip)
+{
+ uint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset;
+ uint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset;
+
+ uint64_t *dst64 = (uint64_t *)dst;
+ uint64_t *src64 = (uint64_t *)src;
+
+ TRACE("[Thread %2u] mov (64 <- 128)\n", p->thread_id);
+
+ dst64[0] = src64[1];
+}
+
static inline void
__instr_mov_128_32_exec(struct rte_swx_pipeline *p __rte_unused,
struct thread *t,
@@ -2701,6 +2737,22 @@ __instr_mov_128_32_exec(struct rte_swx_pipeline *p __rte_unused,
dst32[3] = src32[0];
}
+static inline void
+__instr_mov_32_128_exec(struct rte_swx_pipeline *p __rte_unused,
+ struct thread *t,
+ const struct instruction *ip)
+{
+ uint8_t *dst = t->structs[ip->mov.dst.struct_id] + ip->mov.dst.offset;
+ uint8_t *src = t->structs[ip->mov.src.struct_id] + ip->mov.src.offset;
+
+ uint32_t *dst32 = (uint32_t *)dst;
+ uint32_t *src32 = (uint32_t *)src;
+
+ TRACE("[Thread %2u] mov (32 <- 128)\n", p->thread_id);
+
+ dst32[0] = src32[3];
+}
+
static inline void
__instr_mov_i_exec(struct rte_swx_pipeline *p __rte_unused,
struct thread *t,
--
2.34.1
next prev parent reply other threads:[~2024-02-13 16:58 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 16:57 [PATCH 0/3] pipeline: extend the IPv6 support Cristian Dumitrescu
2024-02-13 16:57 ` [PATCH 1/3] pipeline: add new instruction for upper half of IPv6 address Cristian Dumitrescu
2024-02-13 16:57 ` Cristian Dumitrescu [this message]
2024-02-13 16:57 ` [PATCH 3/3] examples/pipeline: add example for IPv6 address swap Cristian Dumitrescu
2024-02-19 0:46 ` [PATCH 0/3] pipeline: extend the IPv6 support Thomas Monjalon
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