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Sat, 17 Feb 2024 21:11:49 -0800 From: Itamar Gozlan To: , , , , , , , Dariusz Sosnowski , Ori Kam , Matan Azrad CC: Subject: [v2 04/10] net/mlx5/hws: reordering the STE fields to improve hash Date: Sun, 18 Feb 2024 07:11:18 +0200 Message-ID: <20240218051125.717011-4-igozlan@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240218051125.717011-1-igozlan@nvidia.com> References: <20240213095038.451299-9-igozlan@nvidia.com> <20240218051125.717011-1-igozlan@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|MN0PR12MB5930:EE_ X-MS-Office365-Filtering-Correlation-Id: f772939d-fa25-4b8d-9344-08dc30401e8d X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vDrQZO4fHaG0ClzZ/kRQa+y3n79AZtA8vvqV+3oQchmnmJyXKfGZf+8II5gU7+ob59D8zVa+t1Hny8DxHuqBQh+ghTgY+m/JSL1QXoUwJgF6Pm48DbI58wzdJ0xuDciwN5KSTZxDxdF0+IoXyBtKQuTkB84YO8Iks0Bqax6tQsCOoTQq/Kjo8URaDTBkZg1tmwbYBZacgb7r1+Za+7/c39Z9nJwVd6j0SEnRHLDOhEbIV9bukZm7WIy8W56kcw84yKG+6BRci+QfgWgYNQk+MW3zY8MPYdr6QY5bxuSpOJCsYT4iX6+2+3sXvdkoU8mxhEe/G+1xk8Z7mS7GqQOYX56Pa6cxYMldVs3K4C1en7a8ZiFV6OJaWJDJ6gxx7T+AAxJB1i2G7hwa3oUSA0/B9wF3f5+jiE42SVWWuiWRi1iedpLLzjWfvZkNTeoMPSmjRkMURfR8k/J6F6gW0Fu9YFp6kw3uHvqs742iIeo6oL5w4qVHTl2eooFpXejKsTzopL5NCMySKm4xF4We6GOFy1xNRUGsqUG3X6FnyIC0tob6irlwgvSXgc0LuEpeTNtz1ZQ4wVLWE94zeG4iwriwS5CP1sSE+LynG+IhvVZZvYRkETWUDr2tgWpcpczMi5hF+FwyomBWTxjt/k4zUmC/z+MZn2aY3b0CHP1O1o9XYtQ= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(346002)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(36860700004)(64100799003)(186009)(82310400011)(40470700004)(46966006)(2616005)(921011)(36756003)(426003)(336012)(6286002)(83380400001)(26005)(1076003)(70206006)(8676002)(4326008)(8936002)(70586007)(41300700001)(478600001)(6666004)(7696005)(110136005)(316002)(86362001)(356005)(7636003)(6636002)(82740400003)(5660300002)(55016003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2024 05:11:52.7152 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f772939d-fa25-4b8d-9344-08dc30401e8d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5930 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Inserting two rules with the same hash calculation result into the same matcher will cause collisions, which can cause degradation in PPS. Changing the order of some fields in the STE can change the hash result, and doing this for every value would give us a different hash distribution for the inputs. By using precomputed optimal DW locations, we can change the STE order for a limited set of the most common values to reduce the number of hash collisions and improve latency. Signed-off-by: Itamar Gozlan Acked-by: Matan Azrad --- drivers/net/mlx5/hws/mlx5dr_definer.c | 64 +++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index e564062313..eb788a772a 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -100,6 +100,33 @@ __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ __mlx5_mask(typ, fld)) +#define MAX_ROW_LOG 31 + +enum header_layout { + MLX5DR_HL_IPV4_SRC = 64, + MLX5DR_HL_IPV4_DST = 65, + MAX_HL_PRIO, +}; + +/* Each row (i) indicates a different matcher size, and each column (j) + * represents {DW5, DW4, DW3, DW2, DW1, DW0}. + * For values 0,..,2^i, and j (DW) 0,..,5: optimal_dist_dw[i][j] is 1 if the + * number of different hash results on these values equals 2^i, meaning this + * DW hash distribution is complete. + */ +int optimal_dist_dw[MAX_ROW_LOG][DW_SELECTORS_MATCH] = { + {1, 1, 1, 1, 1, 1}, {0, 1, 1, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, + {1, 0, 1, 0, 1, 0}, {0, 0, 0, 1, 1, 0}, {0, 1, 1, 0, 1, 0}, + {0, 0, 0, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 0, 0}, + {1, 0, 1, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 1, 0, 1, 0, 0}, + {1, 0, 0, 0, 0, 0}, {0, 0, 1, 0, 0, 1}, {1, 1, 1, 0, 0, 0}, + {1, 1, 1, 0, 1, 0}, {0, 0, 1, 1, 0, 0}, {0, 1, 1, 0, 0, 1}, + {0, 0, 1, 0, 0, 1}, {0, 0, 1, 0, 0, 0}, {1, 0, 1, 1, 0, 0}, + {1, 0, 1, 0, 0, 1}, {0, 0, 1, 1, 0, 1}, {1, 1, 1, 0, 0, 0}, + {0, 1, 0, 1, 0, 1}, {0, 0, 0, 0, 0, 1}, {0, 0, 0, 1, 1, 1}, + {0, 0, 1, 0, 0, 1}, {1, 1, 0, 1, 1, 0}, {0, 0, 0, 0, 1, 0}, + {0, 0, 0, 1, 1, 0}}; + struct mlx5dr_definer_sel_ctrl { uint8_t allowed_full_dw; /* Full DW selectors cover all offsets */ uint8_t allowed_lim_dw; /* Limited DW selectors cover offset < 64 */ @@ -3185,6 +3212,37 @@ mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer, return rte_errno; } +static void mlx5dr_definer_optimize_order(struct mlx5dr_definer *definer, int num_log) +{ + uint8_t hl_prio[MAX_HL_PRIO - 1] = {MLX5DR_HL_IPV4_SRC, + MLX5DR_HL_IPV4_DST, + MAX_HL_PRIO}; + int dw = 0, i = 0, j; + int *dw_flag; + uint8_t tmp; + + dw_flag = optimal_dist_dw[num_log]; + + while (hl_prio[i] != MAX_HL_PRIO) { + j = 0; + /* Finding a candidate to improve its hash distribution */ + while (j < DW_SELECTORS_MATCH && (hl_prio[i] != definer->dw_selector[j])) + j++; + + /* Finding a DW location with good hash distribution */ + while (dw < DW_SELECTORS_MATCH && dw_flag[dw] == 0) + dw++; + + if (dw < DW_SELECTORS_MATCH && j < DW_SELECTORS_MATCH) { + tmp = definer->dw_selector[dw]; + definer->dw_selector[dw] = definer->dw_selector[j]; + definer->dw_selector[j] = tmp; + dw++; + } + i++; + } +} + static int mlx5dr_definer_find_best_match_fit(struct mlx5dr_context *ctx, struct mlx5dr_definer *definer, @@ -3355,6 +3413,12 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher, goto free_fc; } + if (!mlx5dr_definer_is_jumbo(match_definer) && + !mlx5dr_matcher_req_fw_wqe(matcher) && + !mlx5dr_matcher_is_resizable(matcher) && + !mlx5dr_matcher_is_insert_by_idx(matcher)) + mlx5dr_definer_optimize_order(match_definer, matcher->attr.rule.num_log); + /* Find the range definer layout for match templates fcrs */ ret = mlx5dr_definer_find_best_range_fit(range_definer, matcher); if (ret) { -- 2.39.3