From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D72C843B74; Thu, 22 Feb 2024 12:09:24 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5CD8E40281; Thu, 22 Feb 2024 12:09:02 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 4F1D940EDC for ; Thu, 22 Feb 2024 12:08:56 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9BLbX021847 for ; Thu, 22 Feb 2024 03:08:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=RQ3xOtKML/uoMnSJWUzyVjyiK/ZrER7+usht+w+yeiw=; b=lXD NvJlESkQokWU1x7ZeUW8alBe+rhWGF4nrPXAmtD8yqPoLhPxKV3rVzA5LRhDlkbe TCX4+0TK958YtNAQdcfn2BauJUuLdjRcT8nkMHKRsypuI+u3ypTdzN4rz5qoyEiV CmKpHY9qcaOYvNAQTC8tJHL1Q+KiUwIJO5ONm+EKK58iRAlAKLazKeON9LKq60VM iqYURZkAx6Tj/07a0/dO2Abat6ghh3+brC969ybIZpdUJNjBbx3BHmy+yll+uxuk x8m6fiehum/us+i5HqTbWUA1C6pDG+ruHFDv2IygpFW6GrVPQ18Xr8X2ekgsqm6C 5XXDIfwfLJWmWMJi4dA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dw8at4-14 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 22 Feb 2024 03:08:55 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 03:03:14 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 03:03:14 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id CCB633F71DD; Thu, 22 Feb 2024 03:03:12 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Rahul Bhansali Subject: [PATCH v4 14/14] net/cnxk: reset mbuf fields in multi-seg Tx path Date: Thu, 22 Feb 2024 16:32:32 +0530 Message-ID: <20240222110232.2342903-14-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222110232.2342903-1-ndabilpuram@marvell.com> References: <20240208085956.1741174-1-ndabilpuram@marvell.com> <20240222110232.2342903-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: hSuplaOgsEWPXbra3nkTYmKgTDp61eHU X-Proofpoint-ORIG-GUID: hSuplaOgsEWPXbra3nkTYmKgTDp61eHU X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_09,2024-02-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Rahul Bhansali Currently in debug mode when a buffer is allocated in SW, nb_segs will have invalid values as it didn't come from driver Rx path. Hence reset mbuf next and nb_segs fields in multi-seg Tx path. Fixes: 3626d5195d49 ("net/cnxk: add multi-segment Tx for CN10K") Signed-off-by: Rahul Bhansali --- drivers/net/cnxk/cn10k_tx.h | 2 ++ drivers/net/cnxk/cn9k_tx.h | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h index ad4cbf7ffa..94bfebf246 100644 --- a/drivers/net/cnxk/cn10k_tx.h +++ b/drivers/net/cnxk/cn10k_tx.h @@ -1324,6 +1324,7 @@ cn10k_nix_prepare_mseg(struct cn10k_eth_txq *txq, nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; + m->nb_segs = 1; slist = &cmd[3 + off + 1]; cookie = RTE_MBUF_DIRECT(m) ? m : rte_mbuf_from_indirect(m); @@ -1869,6 +1870,7 @@ cn10k_nix_prepare_mseg_vec_list(struct rte_mbuf *m, uint64_t *cmd, nb_segs = m->nb_segs - 1; m_next = m->next; m->next = NULL; + m->nb_segs = 1; m = m_next; /* Fill mbuf segments */ do { diff --git a/drivers/net/cnxk/cn9k_tx.h b/drivers/net/cnxk/cn9k_tx.h index e6512471b9..fb5e8c5f56 100644 --- a/drivers/net/cnxk/cn9k_tx.h +++ b/drivers/net/cnxk/cn9k_tx.h @@ -643,6 +643,10 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, rte_io_wmb(); #else RTE_SET_USED(cookie); +#endif +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; + m->nb_segs = 1; #endif m = m_next; if (!m) @@ -679,6 +683,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, sg_u = sg->u; slist++; } +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; +#endif m = m_next; } while (nb_segs); @@ -692,6 +699,9 @@ cn9k_nix_prepare_mseg(struct cn9k_eth_txq *txq, segdw += (off >> 1) + 1 + !!(flags & NIX_TX_OFFLOAD_TSTAMP_F); send_hdr->w0.sizem1 = segdw - 1; +#ifdef RTE_ENABLE_ASSERT + rte_io_wmb(); +#endif return segdw; } @@ -908,6 +918,10 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, RTE_SET_USED(cookie); #endif +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; + m->nb_segs = 1; +#endif m = m_next; /* Fill mbuf segments */ do { @@ -938,6 +952,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, sg_u = sg->u; slist++; } +#ifdef RTE_ENABLE_ASSERT + m->next = NULL; +#endif m = m_next; } while (nb_segs); @@ -953,6 +970,9 @@ cn9k_nix_prepare_mseg_vec_list(struct cn9k_eth_txq *txq, !!(flags & NIX_TX_OFFLOAD_TSTAMP_F); send_hdr->w0.sizem1 = segdw - 1; +#ifdef RTE_ENABLE_ASSERT + rte_io_wmb(); +#endif return segdw; } -- 2.25.1