From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F45B43B74; Thu, 22 Feb 2024 12:08:51 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7568840EF0; Thu, 22 Feb 2024 12:08:51 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 608C240ECF; Thu, 22 Feb 2024 12:08:49 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9BLbB021847; Thu, 22 Feb 2024 03:08:48 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=qO+uUIADDnZPHqQj5+K/18uqxv2EHcCCUr1r2dttMg8=; b=Qs0 zRMvdXBFVTjGi4mL/u1BXuY/DsKQ5ezSm4Dbxdft+oHKhE5GWR3hxZOtmdIe7bQi FNoV1ghoTQ6O9nOPntnwl6pqHZOM6VEKtpPdasFvuyGaQ2HnuE9hYcsYM/a29lyN AIleYCA7wx+mrynAF4q1haotBX70dnMBbq/Rnp90X9jvfYSu1EUzhwpdUsVKgOCw MpT47CL8EE/cRQaEY88tCF1FXFmKrPHpSAMzWHlUsnaSV0Z3p0hPjbjZlEi5i1hk nlR5tv4hLkMZEYRNE/7k1q/u6VNMIU12H1e/G3KQpJRsbL7Y23XP2aGCnYJjauS9 tvRf+GLppAQlljWCtvA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dw8as2-5 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 03:08:40 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 03:02:58 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 03:02:58 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C5ACD3F71DD; Thu, 22 Feb 2024 03:02:56 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v4 08/14] net/cnxk: fix max MTU limit Date: Thu, 22 Feb 2024 16:32:26 +0530 Message-ID: <20240222110232.2342903-8-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222110232.2342903-1-ndabilpuram@marvell.com> References: <20240208085956.1741174-1-ndabilpuram@marvell.com> <20240222110232.2342903-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: r_ENWrqQibLnGoqHs5Vozu9W1gZjxZH_ X-Proofpoint-ORIG-GUID: r_ENWrqQibLnGoqHs5Vozu9W1gZjxZH_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_09,2024-02-22_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org From: Sunil Kumar Kori Device can support maximum frame size up to 9212 bytes. While configuring mtu, overhead is considered as ethernet header size, crc and 2 * (vlan tags) which translates to 26 bytes. Exposed overhead to the user via rte_eth_dev_info() is 18 bytes which were leading to set wrong Rx frame size. Fixes: 8589ec212e80 ("net/cnxk: support MTU set") Cc: stable@dpdk.org Signed-off-by: Sunil Kumar Kori --- drivers/net/cnxk/cnxk_ethdev_ops.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c index 4962f3bced..56049c5dd2 100644 --- a/drivers/net/cnxk/cnxk_ethdev_ops.c +++ b/drivers/net/cnxk/cnxk_ethdev_ops.c @@ -20,8 +20,7 @@ cnxk_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; devinfo->max_mac_addrs = dev->max_mac_entries; devinfo->max_vfs = pci_dev->max_vfs; - devinfo->max_mtu = devinfo->max_rx_pktlen - - (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN); + devinfo->max_mtu = devinfo->max_rx_pktlen - CNXK_NIX_L2_OVERHEAD; devinfo->min_mtu = devinfo->min_rx_bufsize - CNXK_NIX_L2_OVERHEAD; devinfo->rx_offload_capa = dev->rx_offload_capa; -- 2.25.1