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Mon, 26 Feb 2024 05:03:35 -0800 From: Michael Baum To: CC: Matan Azrad , Dariusz Sosnowski , Raslan Darawsheh , Viacheslav Ovsiienko , Ori Kam , Suanming Mou Subject: [PATCH v6 3/3] net/mlx5/hws: add compare ESP sequence number support Date: Mon, 26 Feb 2024 15:03:24 +0200 Message-ID: <20240226130324.2981025-4-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226130324.2981025-1-michaelba@nvidia.com> References: <20240214073015.2060103-1-michaelba@nvidia.com> <20240226130324.2981025-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A100:EE_|DM6PR12MB4313:EE_ X-MS-Office365-Filtering-Correlation-Id: ff80e11a-1a96-4b50-b46d-08dc36cb69af X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WbGncPGZ6y3QAE24qSqX3sbKQRvidwRGCkVT0kUD5WwXm52eAYI9DTNHa8WCsx6bc4qbuM/bq9vYIpFIIuXSfErpY/ZpJyjtavGFeD9rzhZ//izPcJs05MQSiM1lwS6R+wENfSGDOcByZ0ABCdGtDIfCO0KmjFg1NUJHoVYb5Z4B6KqUNb5bZdPXMgcwCjc5L77StCE+kK62PQnghFAdtpuwRG4Rrp4oC/GC+adrms7BdKmfyyWXs2OX/eWnmhnZlYw7RC4H4cnWVZpx+JF5vcEO67FB04sWbxFuwyPpTvw+kZGri6tSR22pHl8eeqg04hztbxJvTPSNcP3r8f9CCdtZTKbfnHGl+V9jxIMZaPEyv3VEZZhPnXNKqhH3gS9YG1bcY71T7OrYj2H++5VZonlB4dvlylqy/3Jl5O/nAcA2kMxXSosSZ23ryVVsRV6yTfMxaejvTjHfDh9RQLsWqbKCRV577fgSnfIzoMxTS+o1UzYaKazELEABukkqGHWYY9WW04YO0+mxkPgvHim6RKK2JFfPzPkLDdH+P/s3SCaBvHZjagCr1DF3QFB/O70wE+n42iu8WNWOBjL06unvmZgbWPp4VL45fCPYQQRTeEerMKWFOvO0yU5LnmxvxXlp7s9FliXxKkESH5keOcnEJxrephUC9JoIksP4vofz0+Osj+7la4hkI0tta4UwgfbUMaXQ8Qm41h8YQ9+vAWbTV92x4RFNsqCGFatbALAVQ2Vle18hOwshhRZM4xfS9u5v X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Signed-off-by: Michael Baum Acked-by: Suanming Mou --- doc/guides/nics/mlx5.rst | 1 + drivers/net/mlx5/hws/mlx5dr_definer.c | 22 ++++++++++++++++++++-- drivers/net/mlx5/mlx5_flow_hw.c | 3 +++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index c0a5768117..d7bf81161e 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -434,6 +434,7 @@ Limitations - Only single item is supported per pattern template. - Only 32-bit comparison is supported or 16-bits for random field. - Only supported for ``RTE_FLOW_FIELD_META``, ``RTE_FLOW_FIELD_TAG``, + ``RTE_FLOW_FIELD_ESP_SEQ_NUM``, ``RTE_FLOW_FIELD_RANDOM`` and ``RTE_FLOW_FIELD_VALUE``. - The field type ``RTE_FLOW_FIELD_VALUE`` must be the base (``b``) field. - The field type ``RTE_FLOW_FIELD_RANDOM`` can only be compared with diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index da50b64fb4..39269b4ede 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -424,10 +424,20 @@ mlx5dr_definer_compare_base_value_set(const void *item_spec, value = (const uint32_t *)&b->value[0]; - if (a->field == RTE_FLOW_FIELD_RANDOM) + switch (a->field) { + case RTE_FLOW_FIELD_RANDOM: *base = htobe32(*value << 16); - else + break; + case RTE_FLOW_FIELD_TAG: + case RTE_FLOW_FIELD_META: *base = htobe32(*value); + break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + *base = *value; + break; + default: + break; + } MLX5_SET(ste_match_4dw_range_ctrl_dw, ctrl, base0, 1); } @@ -2930,6 +2940,14 @@ mlx5dr_definer_conv_item_compare_field(const struct rte_flow_field_data *f, fc->compare_idx = dw_offset; DR_CALC_SET_HDR(fc, random_number, random_number); break; + case RTE_FLOW_FIELD_ESP_SEQ_NUM: + fc = &cd->fc[MLX5DR_DEFINER_FNAME_ESP_SEQUENCE_NUMBER]; + fc->item_idx = item_idx; + fc->tag_set = &mlx5dr_definer_compare_set; + fc->tag_mask_set = &mlx5dr_definer_ones_set; + fc->compare_idx = dw_offset; + DR_CALC_SET_HDR(fc, ipsec, sequence_number); + break; default: DR_LOG(ERR, "%u field is not supported", f->field); goto err_notsup; diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index b0e93baaf2..33922bddff 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -6729,6 +6729,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, switch (arg_field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; case RTE_FLOW_FIELD_RANDOM: if (base_field == RTE_FLOW_FIELD_VALUE) @@ -6747,6 +6748,7 @@ flow_hw_item_compare_field_validate(enum rte_flow_field_id arg_field, case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: case RTE_FLOW_FIELD_VALUE: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: break; default: return rte_flow_error_set(error, ENOTSUP, @@ -6763,6 +6765,7 @@ flow_hw_item_compare_width_supported(enum rte_flow_field_id field) switch (field) { case RTE_FLOW_FIELD_TAG: case RTE_FLOW_FIELD_META: + case RTE_FLOW_FIELD_ESP_SEQ_NUM: return 32; case RTE_FLOW_FIELD_RANDOM: return 16; -- 2.25.1