From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FD5443BED; Mon, 26 Feb 2024 14:37:08 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A194942E9F; Mon, 26 Feb 2024 14:36:21 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 5EB7940144; Mon, 26 Feb 2024 14:36:15 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q9srZH014455; Mon, 26 Feb 2024 05:36:14 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=eBsYlR1lj45YUiE0MftoKtG/rNJHc+axbLLzKFWHZkE=; b=H1R W+Wai8o9tKnrfyUSBQlvWFCIcCvRgigi2lxBYVMxb7LeI8uOeZzKuNzNo9Uhe4NP IIedspwkgwKf3H2GW5eCo8sPCAVK966l7xCWVfJ2cQ9s62ojXVIdVAUqaKP/Bnj2 6HT8uL+DNWdVr0yGSoVWoPOP5Zyf69tvDTtp/VITNf60VUE5AazdAa2kTMeDCNuR Q6kiT2A98eWnIdL7WPjjlvC6csr33rNbAHdC0gMtyaKFUixoNzRo0BNclRG76+UC rYloGiAwpI6KZYbvU8ZXToudh5CjInW1dTI2zFwQEs7+8B8jAHlb8VFYipRo5yxs zJQ7+bPN1aexjMIi2cg== Received: from dc5-exch05.marvell.com ([199.233.59.128]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3wgre8rjbs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Feb 2024 05:36:13 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.1258.12; Mon, 26 Feb 2024 05:36:13 -0800 Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Mon, 26 Feb 2024 05:36:12 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Mon, 26 Feb 2024 05:36:12 -0800 Received: from hyd1588t430.caveonetworks.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 03BB13F703F; Mon, 26 Feb 2024 05:36:09 -0800 (PST) From: Nithin Dabilpuram To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: , Subject: [PATCH v5 12/14] common/cnxk: fix mbox struct attributes Date: Mon, 26 Feb 2024 19:05:34 +0530 Message-ID: <20240226133536.2456406-12-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226133536.2456406-1-ndabilpuram@marvell.com> References: <20240208085956.1741174-1-ndabilpuram@marvell.com> <20240226133536.2456406-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 9nsNxMESNqVI7m9GlYT375clyUGbHPQf X-Proofpoint-GUID: 9nsNxMESNqVI7m9GlYT375clyUGbHPQf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_09,2024-02-26_01,2023-05-22_02 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org IO attribute is needed to mbox structs to avoid unaligned or pair access causing by compiler optimization. Add them to structs where it is missing. Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions") Fixes: ddf955d3917e ("common/cnxk: support CPT second pass") Cc: stable@dpdk.org Signed-off-by: Nithin Dabilpuram --- drivers/common/cnxk/roc_mbox.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index 4b4f48e372..d8a8494ac4 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -1427,12 +1427,12 @@ struct nix_cn10k_aq_enq_req { struct nix_cn10k_aq_enq_rsp { struct mbox_msghdr hdr; union { - struct nix_cn10k_rq_ctx_s rq; - struct nix_cn10k_sq_ctx_s sq; - struct nix_cq_ctx_s cq; - struct nix_rsse_s rss; - struct nix_rx_mce_s mce; - struct nix_band_prof_s prof; + __io struct nix_cn10k_rq_ctx_s rq; + __io struct nix_cn10k_sq_ctx_s sq; + __io struct nix_cq_ctx_s cq; + __io struct nix_rsse_s rss; + __io struct nix_rx_mce_s mce; + __io struct nix_band_prof_s prof; }; }; @@ -1668,11 +1668,11 @@ struct nix_rq_cpt_field_mask_cfg_req { #define RQ_CTX_MASK_MAX 6 union { uint64_t __io rq_ctx_word_set[RQ_CTX_MASK_MAX]; - struct nix_cn10k_rq_ctx_s rq_set; + __io struct nix_cn10k_rq_ctx_s rq_set; }; union { uint64_t __io rq_ctx_word_mask[RQ_CTX_MASK_MAX]; - struct nix_cn10k_rq_ctx_s rq_mask; + __io struct nix_cn10k_rq_ctx_s rq_mask; }; struct nix_lf_rx_ipec_cfg1_req { uint32_t __io spb_cpt_aura; -- 2.25.1