From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1878743C2C; Wed, 28 Feb 2024 16:11:53 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2530E4340E; Wed, 28 Feb 2024 16:11:29 +0100 (CET) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2085.outbound.protection.outlook.com [40.107.100.85]) by mails.dpdk.org (Postfix) with ESMTP id 5CF44433FF for ; Wed, 28 Feb 2024 16:11:23 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Fyr2562UzhX6sqOAQHOUVEbiZrPr8XoqiW0S+8xbPEENo024Xhg+21tPduVIPMm+c1JMpy9YmmpG4KPoZO0b5qYRhKgObGXDGGRhqVqZOtahpNlAVhkpxni6PO359UG5OMcdPtuXjw7Ic9Qvv1xIBTd4g/t6NIlMMa5jywJkh6EqivT/KCvktNbJg7WGJ/q7y2T3WVFJzinbyAlFfzgZaZEFHHw46lA60bNLHIonf8rUD2HRUdV2VN3GF9L0jA5r6SPWRy2vRYMD24V0+K92wPO91l4ZLC33A+RJvhcC7kmRse6XyOt5SwfyXsci8txctTciPgsvffL59hxowHVB8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=MXaIc+tAYhR/etArB7olbapgpohR4FaymWpLX6JdoXY=; b=BS5/3fArTQDf6YfMbxlYFka7Hk7QFabkKqSKauKQXprLhAYJn4x3O/+mq7oNyuLBOHyMCKNGnK/Eq4bISOYyb5bevCspqXU9yJ9gm02IEbyzUkKddCXXGST3fj6eGGq+C/N2FVjHgGuc3aLPOtG/jesowh6oJofir02gx3734NPFAfovoFoUw66XQ89k69RxnV0Ap48w4zQdOvfRoMk2Ry3BmMTKzuaPNNpW4giB9AI2qsrXbJ8Q9hgHyV+d0m3SF4f9bSCZnju9MBbnKe3aCiLJ6Id3hxNVZAjhAcjZ3VZ+syGAgGpjSJkRynkc6It9QrXEtoB6S/+sPHl8GissyA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=MXaIc+tAYhR/etArB7olbapgpohR4FaymWpLX6JdoXY=; b=O+Jnf3Qa+3pRua4z0VlMPFMHZL0IXd2baZVTxqnWvZAgWrX/b8epf5pIhHmH5a344vXxBEF3ZCDx7wQ0zQBn4cSTE+uB7sux4z1xFJ8RY6f3Obb6/4Zxv80qXjO/pkCjFtNMt7OhZWE5xSI2M5F+ucmnecRxEgRDEwMAGBkz61D1Zf+L14YuV12nAptGUp+1bbjJdUwWnsoZGtG70fcL6nR/KNypfiRN8wvPk7yD6Xjm1CRISvFYd+7HWxhjduBrLw6uO/YqIyG3UoRLNy03BfMoRiQ96jyqejxTjKFMLSs1j2spLlbPG2Kug9aC6ynkBP/DGuuqdmXbrsrOSDRvBw== Received: from BYAPR05CA0028.namprd05.prod.outlook.com (2603:10b6:a03:c0::41) by CH2PR12MB4309.namprd12.prod.outlook.com (2603:10b6:610:a4::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7316.41; Wed, 28 Feb 2024 15:11:20 +0000 Received: from MWH0EPF000971E7.namprd02.prod.outlook.com (2603:10b6:a03:c0:cafe::b3) by BYAPR05CA0028.outlook.office365.com (2603:10b6:a03:c0::41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7362.12 via Frontend Transport; Wed, 28 Feb 2024 15:11:19 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by MWH0EPF000971E7.mail.protection.outlook.com (10.167.243.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.25 via Frontend Transport; Wed, 28 Feb 2024 15:11:19 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Wed, 28 Feb 2024 07:11:01 -0800 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Wed, 28 Feb 2024 07:10:57 -0800 From: Bing Zhao To: , , , , , , , , , CC: , Subject: [PATCH v4 5/5] net/mlx5: validate the actions combination with NAT64 Date: Wed, 28 Feb 2024 17:09:13 +0200 Message-ID: <20240228150913.32603-6-bingz@nvidia.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240228150913.32603-1-bingz@nvidia.com> References: <20231227090731.2569427-1-bingz@nvidia.com> <20240228150913.32603-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E7:EE_|CH2PR12MB4309:EE_ X-MS-Office365-Filtering-Correlation-Id: 02a8b839-80b6-4bf4-eaaa-08dc386f8480 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mLBRGpofY31ylZFmthfHKYkuUgvxsNsR60++q7tnwo9cjfzbILAbe7wgLh98Q/cRyv12cLtwnkQVaRmGuWy8je/gyU0XqqXysbA+wKUqpWcGj2fbsmjc+YRzf9XOZxyS8xzj0yEOZHkJIqHDe2SJSXDVWJxA0bOJtkmgWa5PFqCcAnE7+Er9aZLs7r46AgqSkzYj9wdOpi0snZftj/cd4757jKJqo30pqgE/mpnJPUf/qFTT8ll3k4bbGzsOcfySyoYksS/7q23ZLx8vOshVzH4yPit6YbOAtitAPJp7ibbOBBS4OOTz5JAFBaVGE0P3KJkttrYh0rHqiBuQAZX3jpyPIOalpFGS5y5bqyexBFv5YvIK3KyLoX2o3XUCgT760zct1cMuqJPUu/SRplSXQfqdiIRQyfpP8C1cOqT6QtoC1mvJZb/PqIyRetWp2Ad/vrnRBVhR5G9NJb77Z5ZYQ4La4Vb3d4NEpaKph9N5SBt+qCyE3DzUxWCFSauaM+IWT+je7EfiWEdixk1nplC3TdHFlCz4CQ1nMqQF2eypgEKme9PtAGeO21U9/CI33L+ZOdh9fsuXh7YmsYKRwAWm1LqysvuMdZUNi4f4DXYtkizrc2PZVkEh/rUwjxWPIJjO3l+FiFLpaNjzMWKv3K4xS5a4Sk9eODF0hTB9axCD1ao+NwypFgoNK/MLPRWEZARJVIEIZ57EVgfZ/SLwzdtt+C34iRgGJdNAKJcB13y2yETO6G4VLbBih/GraM3lMT5fI7SvBQccuHc/q13RN231fQ== X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230031)(36860700004)(82310400014)(921011); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2024 15:11:19.2677 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02a8b839-80b6-4bf4-eaaa-08dc386f8480 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4309 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org NAT64 is treated as a modify header action. The action order and limitation should be the same as that of modify header in each domain. Since the last 2 TAG registers will be used implicitly in the address backup mode, the values in these registers are no longer valid after the NAT64 action. The application should not try to match these TAGs after the rule that contains NAT64 action. Signed-off-by: Bing Zhao --- drivers/net/mlx5/mlx5_flow.h | 1 + drivers/net/mlx5/mlx5_flow_hw.c | 51 +++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 897a283716..ea428a8c21 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -392,6 +392,7 @@ enum mlx5_feature_name { #define MLX5_FLOW_ACTION_PORT_REPRESENTOR (1ull << 47) #define MLX5_FLOW_ACTION_IPV6_ROUTING_REMOVE (1ull << 48) #define MLX5_FLOW_ACTION_IPV6_ROUTING_PUSH (1ull << 49) +#define MLX5_FLOW_ACTION_NAT64 (1ull << 50) #define MLX5_FLOW_DROP_INCLUSIVE_ACTIONS \ (MLX5_FLOW_ACTION_COUNT | MLX5_FLOW_ACTION_SAMPLE | MLX5_FLOW_ACTION_AGE) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index f32bdff98f..7730bcab6f 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -5866,6 +5866,50 @@ flow_hw_validate_action_default_miss(struct rte_eth_dev *dev, return 0; } +static int +flow_hw_validate_action_nat64(struct rte_eth_dev *dev, + const struct rte_flow_actions_template_attr *attr, + const struct rte_flow_action *action, + const struct rte_flow_action *mask, + uint64_t action_flags, + struct rte_flow_error *error) +{ + struct mlx5_priv *priv = dev->data->dev_private; + const struct rte_flow_action_nat64 *nat64_c; + enum rte_flow_nat64_type cov_type; + + RTE_SET_USED(action_flags); + if (mask->conf && ((const struct rte_flow_action_nat64 *)mask->conf)->type) { + nat64_c = (const struct rte_flow_action_nat64 *)action->conf; + cov_type = nat64_c->type; + if ((attr->ingress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][cov_type]) || + (attr->egress && !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][cov_type]) || + (attr->transfer && !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][cov_type])) + goto err_out; + } else { + /* + * Usually, the actions will be used on both directions. For non-masked actions, + * both directions' actions will be checked. + */ + if (attr->ingress) + if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_6TO4] || + !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_RX][RTE_FLOW_NAT64_4TO6]) + goto err_out; + if (attr->egress) + if (!priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_6TO4] || + !priv->action_nat64[MLX5DR_TABLE_TYPE_NIC_TX][RTE_FLOW_NAT64_4TO6]) + goto err_out; + if (attr->transfer) + if (!priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_6TO4] || + !priv->action_nat64[MLX5DR_TABLE_TYPE_FDB][RTE_FLOW_NAT64_4TO6]) + goto err_out; + } + return 0; +err_out: + return rte_flow_error_set(error, EOPNOTSUPP, RTE_FLOW_ERROR_TYPE_ACTION, + NULL, "NAT64 action is not supported."); +} + static int mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, const struct rte_flow_actions_template_attr *attr, @@ -6066,6 +6110,13 @@ mlx5_flow_hw_actions_validate(struct rte_eth_dev *dev, MLX5_HW_VLAN_PUSH_VID_IDX; action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN; break; + case RTE_FLOW_ACTION_TYPE_NAT64: + ret = flow_hw_validate_action_nat64(dev, attr, action, mask, + action_flags, error); + if (ret != 0) + return ret; + action_flags |= MLX5_FLOW_ACTION_NAT64; + break; case RTE_FLOW_ACTION_TYPE_END: actions_end = true; break; -- 2.39.3