From: <shaibran@amazon.com>
To: <ferruh.yigit@amd.com>
Cc: <dev@dpdk.org>, Shai Brandes <shaibran@amazon.com>
Subject: [PATCH v2 12/33] net/ena/hal: rename fields in completion descriptors
Date: Mon, 4 Mar 2024 14:29:21 +0200 [thread overview]
Message-ID: <20240304122942.3496-13-shaibran@amazon.com> (raw)
In-Reply-To: <20240304122942.3496-1-shaibran@amazon.com>
From: Shai Brandes <shaibran@amazon.com>
Several reserved bits in ena_eth_io_tx_cdesc and
ena_eth_io_rx_cdesc_base have been renamed explicitly to
MBZ (Must Be Zero).
These bits are set by the device to zero before being sent
to the driver. The fields are used as an integrity check in
order to ensure that the received descriptor is not corrupted.
Signed-off-by: Shai Brandes <shaibran@amazon.com>
Reviewed-by: Amit Bernstein <amitbern@amazon.com>
---
drivers/net/ena/hal/ena_defs/ena_admin_defs.h | 1 +
.../net/ena/hal/ena_defs/ena_eth_io_defs.h | 49 +++++++++++++++++--
2 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h
index 670e794c98..438e4a1085 100644
--- a/drivers/net/ena/hal/ena_defs/ena_admin_defs.h
+++ b/drivers/net/ena/hal/ena_defs/ena_admin_defs.h
@@ -84,6 +84,7 @@ enum ena_admin_aq_caps_id {
ENA_ADMIN_ENA_SRD_INFO = 1,
ENA_ADMIN_CUSTOMER_METRICS = 2,
ENA_ADMIN_EXTENDED_RESET_REASONS = 3,
+ ENA_ADMIN_CDESC_MBZ = 4,
};
enum ena_admin_placement_policy_type {
diff --git a/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h b/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h
index 2107d17fdf..f811dd261e 100644
--- a/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h
+++ b/drivers/net/ena/hal/ena_defs/ena_eth_io_defs.h
@@ -152,7 +152,8 @@ struct ena_eth_io_tx_cdesc {
/* flags
* 0 : phase
- * 7:1 : reserved1
+ * 5:1 : reserved1
+ * 7:6 : mbz6 - MBZ
*/
uint8_t flags;
@@ -198,7 +199,7 @@ struct ena_eth_io_rx_desc {
struct ena_eth_io_rx_cdesc_base {
/* 4:0 : l3_proto_idx
* 6:5 : src_vlan_cnt
- * 7 : reserved7 - MBZ
+ * 7 : mbz7 - MBZ
* 12:8 : l4_proto_idx
* 13 : l3_csum_err - when set, either the L3
* checksum error detected, or, the controller didn't
@@ -214,7 +215,8 @@ struct ena_eth_io_rx_cdesc_base {
* 16 : l4_csum_checked - L4 checksum was verified
* (could be OK or error), when cleared the status of
* checksum is unknown
- * 23:17 : reserved17 - MBZ
+ * 17 : mbz17 - MBZ
+ * 23:18 : reserved18
* 24 : phase
* 25 : l3_csum2 - second checksum engine result
* 26 : first - Indicates first descriptor in
@@ -341,6 +343,8 @@ struct ena_eth_io_numa_node_cfg_reg {
/* tx_cdesc */
#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
+#define ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT 6
+#define ENA_ETH_IO_TX_CDESC_MBZ6_MASK GENMASK(7, 6)
/* rx_desc */
#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
@@ -355,6 +359,8 @@ struct ena_eth_io_numa_node_cfg_reg {
#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT 7
+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK BIT(7)
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
@@ -365,6 +371,8 @@ struct ena_eth_io_numa_node_cfg_reg {
#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT 17
+#define ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK BIT(17)
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
@@ -731,6 +739,15 @@ static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p,
p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
}
+static inline uint8_t get_ena_eth_io_tx_cdesc_mbz6(const struct ena_eth_io_tx_cdesc *p)
+{
+ return (p->flags & ENA_ETH_IO_TX_CDESC_MBZ6_MASK) >> ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT;
+}
+static inline void set_ena_eth_io_tx_cdesc_mbz6(struct ena_eth_io_tx_cdesc *p, uint8_t val)
+{
+ p->flags |= (val << ENA_ETH_IO_TX_CDESC_MBZ6_SHIFT) & ENA_ETH_IO_TX_CDESC_MBZ6_MASK;
+}
+
static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)
{
return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
@@ -791,6 +808,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_r
p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
}
+static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz7(const struct ena_eth_io_rx_cdesc_base *p)
+{
+ return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK) >>
+ ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT;
+}
+
+static inline void set_ena_eth_io_rx_cdesc_base_mbz7(struct ena_eth_io_rx_cdesc_base *p,
+ uint32_t val)
+{
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ7_SHIFT) &
+ ENA_ETH_IO_RX_CDESC_BASE_MBZ7_MASK;
+}
+
static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
{
return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
@@ -841,6 +871,19 @@ static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_i
p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK;
}
+static inline uint32_t get_ena_eth_io_rx_cdesc_base_mbz17(const struct ena_eth_io_rx_cdesc_base *p)
+{
+ return (p->status & ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK) >>
+ ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT;
+}
+
+static inline void set_ena_eth_io_rx_cdesc_base_mbz17(struct ena_eth_io_rx_cdesc_base *p,
+ uint32_t val)
+{
+ p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_MBZ17_SHIFT) &
+ ENA_ETH_IO_RX_CDESC_BASE_MBZ17_MASK;
+}
+
static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
{
return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
--
2.17.1
next prev parent reply other threads:[~2024-03-04 12:31 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-04 12:29 [PATCH v2 00/33] net/ena: v2.9.0 driver release shaibran
2024-03-04 12:29 ` [PATCH v2 01/33] net/ena: rework the metrics multi-process functions shaibran
2024-03-04 12:29 ` [PATCH v2 02/33] net/ena: report new supported link speed capabilities shaibran
2024-03-04 12:29 ` [PATCH v2 03/33] net/ena: update imissed stat with Rx overruns shaibran
2024-03-04 12:29 ` [PATCH v2 04/33] net/ena: sub-optimal configuration notifications support shaibran
2024-03-04 12:29 ` [PATCH v2 05/33] net/ena: fix fast mbuf free shaibran
2024-03-04 12:29 ` [PATCH v2 06/33] net/ena: rename base folder to hal shaibran
2024-03-04 12:29 ` [PATCH v2 07/33] net/ena: restructure the llq policy setting process shaibran
2024-03-04 12:29 ` [PATCH v2 08/33] net/ena/hal: exponential backoff exp limit shaibran
2024-03-04 12:29 ` [PATCH v2 09/33] net/ena/hal: add a new csum offload bit shaibran
2024-03-04 12:29 ` [PATCH v2 10/33] net/ena/hal: added a bus parameter to ena memcpy macro shaibran
2024-03-04 12:29 ` [PATCH v2 11/33] net/ena/hal: optimize Rx ring submission queue shaibran
2024-03-04 12:29 ` shaibran [this message]
2024-03-04 12:29 ` [PATCH v2 13/33] net/ena/hal: use correct read once on u8 field shaibran
2024-03-04 12:29 ` [PATCH v2 14/33] net/ena/hal: add completion descriptor corruption check shaibran
2024-03-04 12:29 ` [PATCH v2 15/33] net/ena/hal: malformed Tx descriptor error reason shaibran
2024-03-04 12:29 ` [PATCH v2 16/33] net/ena/hal: phc feature modifications shaibran
2024-03-04 12:29 ` [PATCH v2 17/33] net/ena/hal: restructure interrupt handling shaibran
2024-03-04 12:29 ` [PATCH v2 18/33] net/ena/hal: add unlikely to error checks shaibran
2024-03-04 12:29 ` [PATCH v2 19/33] net/ena/hal: missing admin interrupt reset reason shaibran
2024-03-04 12:29 ` [PATCH v2 20/33] net/ena/hal: check for existing keep alive notification shaibran
2024-03-04 12:29 ` [PATCH v2 21/33] net/ena/hal: modify memory barrier comment shaibran
2024-03-04 12:29 ` [PATCH v2 22/33] net/ena/hal: rework Rx ring submission queue shaibran
2024-03-04 12:29 ` [PATCH v2 23/33] net/ena/hal: remove operating system type enum shaibran
2024-03-04 12:29 ` [PATCH v2 24/33] net/ena/hal: handle command abort shaibran
2024-03-04 12:29 ` [PATCH v2 25/33] net/ena/hal: add support for device reset request shaibran
2024-03-04 12:29 ` [PATCH v2 26/33] net/ena: cosmetic changes shaibran
2024-03-04 12:29 ` [PATCH v2 27/33] net/ena/hal: modify customer metrics memory management shaibran
2024-03-04 12:29 ` [PATCH v2 28/33] net/ena/hal: cosmetic changes shaibran
2024-03-04 12:29 ` [PATCH v2 29/33] net/ena: update device-preferred size of rings shaibran
2024-03-04 12:29 ` [PATCH v2 30/33] net/ena: exhaust interrupt callbacks in device close shaibran
2024-03-04 12:29 ` [PATCH v2 31/33] net/ena: support max large llq depth from the device shaibran
2024-03-04 12:29 ` [PATCH v2 32/33] net/ena: control path pure polling mode shaibran
2024-03-04 12:29 ` [PATCH v2 33/33] net/ena: upgrade driver version to 2.9.0 shaibran
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